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5f589aca37
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Use wishbone interface for CPU port
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2022-07-14 16:05:49 +02:00 |
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5fb8d3a176
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gitignore: ignore __pycache__
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2022-07-14 15:59:32 +02:00 |
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f026fcfe5c
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fix: workaround nextpnr-xilinx#42
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2022-07-14 15:59:32 +02:00 |
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77c602c8fd
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fix: reorganize outputs to 6 strands per PMOD
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2022-07-14 15:59:32 +02:00 |
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99e52e611e
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fix: add license
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2022-06-21 07:21:16 +02:00 |
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cbd72445c0
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doc: add packet structure to README
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2022-06-20 14:13:05 +02:00 |
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7bc99720ba
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chore: clean up makefile, remove unused targets
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2022-06-20 13:24:31 +02:00 |
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07e0cc9f9d
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fix: suppress ghdl binding warnings during synthesis
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2022-06-20 13:16:51 +02:00 |
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87ef826ad2
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fix: work around ghdl#2102
https://github.com/ghdl/ghdl/issues/2102
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2022-06-20 13:15:22 +02:00 |
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e25e8a958d
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fix: work around ghdl#2078
https://github.com/ghdl/ghdl/issues/2078
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2022-06-20 13:15:22 +02:00 |
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498089d468
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fix: work around ghdl#2077
https://github.com/ghdl/ghdl/issues/2077
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2022-06-20 13:15:06 +02:00 |
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a9a1797236
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feat: double buffering
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2022-06-20 13:11:31 +02:00 |
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df30572711
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update ws2812 submodule
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2022-06-20 10:32:36 +02:00 |
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e8476445b2
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fix: use parallel ws2812 driver
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2022-06-18 17:24:47 +02:00 |
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6ff0e77d38
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makefile: make ghdl error on warnings
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2022-06-07 07:34:09 +02:00 |
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645a838a73
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vhdl: use UDP packet length
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2022-06-07 07:34:09 +02:00 |
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70a7b0520a
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vhdl: only run encoders once all pixels are received
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2022-06-07 07:34:09 +02:00 |
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9ca64a7d4d
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Update ws2812 submodule
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2022-06-07 07:34:09 +02:00 |
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0f497e76e8
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vhdl: implement bounds checking for strand number
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2022-06-07 07:34:09 +02:00 |
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fcfa9eb7d0
|
vhdl: workaround ghdl#2080
https://github.com/ghdl/ghdl/issues/2080
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2022-06-07 07:34:09 +02:00 |
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3c5c3a4555
|
vhdl: use big-endian network byte order
liteeth splits the rx data stream into 4-byte chunks and interprets them as
little-endian 32-bit vecs; similar for the other direction.
|
2022-06-07 07:34:09 +02:00 |
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4bced13726
|
vhdl: implement magic number on receive
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2022-06-06 17:11:39 +02:00 |
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904f34f4d4
|
vhdl: implement frame number checking
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2022-06-06 16:45:16 +02:00 |
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4d07ec3fa1
|
vhdl: reorganize receive FSM to avoid ghdl issues
https://github.com/ghdl/ghdl/issues/2077
https://github.com/ghdl/ghdl/issues/2078
|
2022-06-06 15:24:49 +02:00 |
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40caa85d92
|
vhdl: implement multiple strands
|
2022-06-06 12:58:41 +02:00 |
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24e3b11588
|
Use little endian byte order in network streams
|
2022-06-06 10:29:45 +02:00 |
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ccd911dc1e
|
vhdl: implement feedback packets
|
2022-06-05 22:56:29 +02:00 |
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d0e65a3126
|
vhdl: remove unused signals
|
2022-06-05 22:27:16 +02:00 |
|
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79fce1afc1
|
vhdl: disable test UDP sender
|
2022-06-05 21:36:10 +02:00 |
|
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9121ccfdbe
|
vhdl: implement setting LEDs via UDP
|
2022-06-05 21:36:10 +02:00 |
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d5b0ee2cfa
|
vhdl: rename NUM_DRIVERS to NUM_STRANDS
|
2022-06-05 21:36:10 +02:00 |
|
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2ec250e79d
|
vhdl: rename clk_sys to sys_clk
|
2022-06-05 21:36:10 +02:00 |
|
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57e6daedcc
|
vhdl: move ws2812 driver to splink module
|
2022-06-05 21:36:10 +02:00 |
|
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94ff182aec
|
Add README.md
|
2022-06-05 16:36:06 +02:00 |
|
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01fe200d92
|
Pixel UDP port demo
|
2022-06-05 16:35:20 +02:00 |
|
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ba1aa9181e
|
vhdl: add ws2812 demo
|
2022-06-05 13:10:19 +02:00 |
|
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|
ffbe87f1f1
|
Add ws2812 submodule
|
2022-06-05 10:21:44 +02:00 |
|
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de6a38044b
|
vhdl: assert reset if PLL is not locked
|
2022-06-04 21:53:14 +02:00 |
|
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d624673804
|
Add liteeth core
|
2022-06-04 21:51:28 +02:00 |
|
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|
e7087eb7db
|
makefile: switch to nextpnr toolchain
|
2022-06-04 21:19:37 +02:00 |
|
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|
608c17d1a8
|
makefile: use relative paths
|
2022-06-04 21:19:26 +02:00 |
|
|
|
8257886f6b
|
Add nextpnr-xilinx makefile
|
2022-06-04 21:18:57 +02:00 |
|
|
|
63557ba83f
|
fix(Makefile.symbiflow): fix read_verilog yosys command
|
2022-06-03 22:18:09 +02:00 |
|
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|
eedf254b15
|
fix(gen_liteeth): fix configurations
|
2022-06-03 22:17:13 +02:00 |
|
|
|
d6687786a7
|
Add basic tools and VHDL skeleton
|
2022-06-03 19:11:07 +02:00 |
|
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5a9bb94922
|
Initial empty commit
|
2022-05-11 18:15:30 +02:00 |
|
