vhdl: implement frame number checking
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4d07ec3fa1
commit
904f34f4d4
2 changed files with 49 additions and 26 deletions
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@ -190,7 +190,8 @@ architecture a of arty_a7 is
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signal sys_reset : std_logic;
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signal frame_done : std_logic;
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signal frame_number : unsigned(31 downto 0);
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signal prev_frame_number : unsigned(31 downto 0);
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begin
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leds_simple <= (others => '0');
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led0 <= (others => '0');
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@ -299,27 +300,28 @@ begin
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pmod_d <= drivers(23 downto 16);
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sender: process(sys_clk)
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variable frame_counter : unsigned(31 downto 0);
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begin
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if sys_reset then
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frame_counter := (others => '0');
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elsif rising_edge(sys_clk) then
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if pixel_source_valid then
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remote_ip_address <= pixel_source_src_ip_address;
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remote_port <= pixel_source_src_port;
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end if;
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if rising_edge(sys_clk) then
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if sys_reset then
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prev_frame_number <= frame_number;
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else
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if pixel_source_valid then
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remote_ip_address <= pixel_source_src_ip_address;
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remote_port <= pixel_source_src_port;
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end if;
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if frame_done then
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pixel_sink_length <= x"0004";
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pixel_sink_data <= std_logic_vector(frame_counter);
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pixel_sink_valid <= '1';
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pixel_sink_last <= '1';
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if frame_number /= prev_frame_number then
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prev_frame_number <= frame_number;
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frame_counter := frame_counter + 1;
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end if;
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pixel_sink_length <= x"0004";
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pixel_sink_data <= std_logic_vector(frame_number);
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pixel_sink_valid <= '1';
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pixel_sink_last <= '1';
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end if;
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if pixel_sink_ready and pixel_sink_valid then
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pixel_sink_valid <= '0';
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if pixel_sink_ready and pixel_sink_valid then
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pixel_sink_valid <= '0';
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end if;
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end if;
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end if;
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end process;
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@ -337,7 +339,7 @@ begin
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udp_last => pixel_source_last,
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udp_data => pixel_source_data,
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frame_done => frame_done,
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frame_number => frame_number,
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drivers => drivers
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);
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@ -15,7 +15,7 @@ entity splink is
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udp_last : in std_logic;
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udp_data : in std_logic_vector(31 downto 0);
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frame_done : out std_logic;
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frame_number : out unsigned(31 downto 0);
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drivers : out std_logic_vector(NUM_STRANDS-1 downto 0)
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);
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@ -37,9 +37,14 @@ architecture a of splink is
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signal active_strand: natural range 0 to NUM_STRANDS-1;
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signal num_pixels: natural range 1 to MAX_STRAND_LEN;
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signal frame_number: unsigned(31 downto 0);
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signal current_frame: unsigned(31 downto 0);
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signal pixels_received: natural range 0 to MAX_STRAND_LEN-1;
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signal clear_write_flags : std_logic;
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signal all_strands_written : std_logic;
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signal some_strands_written : std_logic;
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type receive_state_t is (FRAME_NUM, STRAND_NUM, DATA, DROP);
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signal receive_state : receive_state_t;
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begin
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@ -85,7 +90,7 @@ begin
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end if;
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end if;
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if frame_done then
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if clear_write_flags then
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led_data_arr(i).was_written <= '0';
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end if;
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end if;
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@ -94,11 +99,14 @@ begin
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process(led_data_arr)
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begin
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frame_done <= '1';
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all_strands_written <= '1';
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some_strands_written <= '0';
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for i in 0 to NUM_STRANDS-1 loop
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if not led_data_arr(i).was_written then
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frame_done <= '0';
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if led_data_arr(i).was_written then
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some_strands_written <= '1';
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else
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all_strands_written <= '0';
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end if;
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end loop;
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end process;
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@ -106,8 +114,16 @@ begin
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fsm: process(clk)
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begin
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if rising_edge(clk) then
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clear_write_flags <= '0';
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if all_strands_written then
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frame_number <= current_frame;
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clear_write_flags <= '1';
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end if;
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if reset then
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receive_state <= STRAND_NUM;
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clear_write_flags <= '1';
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elsif udp_valid then
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if udp_last then
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-- always resynchronize to start of packet
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@ -125,7 +141,12 @@ begin
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receive_state <= FRAME_NUM;
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when FRAME_NUM =>
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frame_number <= unsigned(udp_data);
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if not some_strands_written then
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current_frame <= unsigned(udp_data);
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elsif current_frame /= unsigned(udp_data) then
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current_frame <= unsigned(udp_data);
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clear_write_flags <= '1';
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end if;
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pixels_received <= 0;
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receive_state <= DATA;
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