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VHDL
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608c17d1a8
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Xiretza
608c17d1a8
makefile: use relative paths
2022-06-04 21:19:26 +02:00
vhdl
Add basic tools and VHDL skeleton
2022-06-03 19:11:07 +02:00
.gitignore
Add basic tools and VHDL skeleton
2022-06-03 19:11:07 +02:00
arty_a7_35.xdc
Add basic tools and VHDL skeleton
2022-06-03 19:11:07 +02:00
gen_liteeth.py
fix(gen_liteeth): fix configurations
2022-06-03 22:17:13 +02:00
Makefile
makefile: use relative paths
2022-06-04 21:19:26 +02:00
Makefile.nextpnr
Add nextpnr-xilinx makefile
2022-06-04 21:18:57 +02:00
Makefile.symbiflow
fix(Makefile.symbiflow): fix read_verilog yosys command
2022-06-03 22:18:09 +02:00