Add ws2812 submodule
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[submodule "vhdl/ws2812_vhdl"]
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path = vhdl/ws2812_vhdl
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url = https://gitlab.com/xiretza/ws2812_vhdl
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Makefile
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Makefile
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@ -13,7 +13,7 @@ VHDL_DIR = vhdl
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WORKLIB_NAME = splink
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VHDL_FILES = $(wildcard $(VHDL_DIR)/*.vhdl)
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VHDL_FILES = $(wildcard $(VHDL_DIR)/*.vhdl $(VHDL_DIR)/ws2812_vhdl/*.vhd)
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VERILOG_FILES = $(LITEX_WORKDIR)/gateware/liteeth_core.v
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SBY_FILES =
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Subproject commit 0d1688f1840b8b5894b9f4cd027fcc1653dd3657
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