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01fe200d92
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Xiretza
01fe200d92
Pixel UDP port demo
2022-06-05 16:35:20 +02:00
vhdl
Pixel UDP port demo
2022-06-05 16:35:20 +02:00
.gitignore
Add basic tools and VHDL skeleton
2022-06-03 19:11:07 +02:00
.gitmodules
Add ws2812 submodule
2022-06-05 10:21:44 +02:00
arty_a7_35.xdc
Add liteeth core
2022-06-04 21:51:28 +02:00
gen_liteeth.py
Pixel UDP port demo
2022-06-05 16:35:20 +02:00
Makefile
Add ws2812 submodule
2022-06-05 10:21:44 +02:00
Makefile.nextpnr
Add nextpnr-xilinx makefile
2022-06-04 21:18:57 +02:00
Makefile.symbiflow
fix(Makefile.symbiflow): fix read_verilog yosys command
2022-06-03 22:18:09 +02:00