Commit graph

Select branches

Hide pull requests

liteeth-wishbone

main

Mono Color

• c44e94da5d Add patched liteeth.core module to allow hybrid mode liteeth-wishbone Xiretza 2022-07-14 16:04:40 +0200
• a13569c2eb feat: add blank firmware directory Xiretza 2022-06-30 18:21:06 +0200
• 5f589aca37 Use wishbone interface for CPU port Xiretza 2022-06-30 18:20:36 +0200
• 5fb8d3a176 gitignore: ignore __pycache__ main Xiretza 2022-07-14 15:18:39 +0200
• f026fcfe5c fix: workaround nextpnr-xilinx#42 Xiretza 2022-07-14 14:18:49 +0200
• 77c602c8fd fix: reorganize outputs to 6 strands per PMOD Xiretza 2022-07-14 14:17:55 +0200
• 99e52e611e fix: add license Xiretza 2022-06-21 07:21:16 +0200
• cbd72445c0 doc: add packet structure to README Xiretza 2022-06-20 13:59:01 +0200
• 7bc99720ba chore: clean up makefile, remove unused targets Xiretza 2022-06-20 13:24:31 +0200
• 07e0cc9f9d fix: suppress ghdl binding warnings during synthesis Xiretza 2022-06-20 13:16:51 +0200
• 87ef826ad2 fix: work around ghdl#2102 Xiretza 2022-06-20 11:43:29 +0200
• e25e8a958d fix: work around ghdl#2078 Xiretza 2022-06-20 11:43:01 +0200
• 498089d468 fix: work around ghdl#2077 Xiretza 2022-06-20 13:15:06 +0200
• a9a1797236 feat: double buffering Xiretza 2022-06-20 11:42:17 +0200
• df30572711 update ws2812 submodule Xiretza 2022-06-20 10:32:36 +0200
• e8476445b2 fix: use parallel ws2812 driver Xiretza 2022-06-18 17:24:47 +0200
• 6ff0e77d38 makefile: make ghdl error on warnings Xiretza 2022-06-06 20:49:53 +0200
• 645a838a73 vhdl: use UDP packet length Xiretza 2022-06-06 18:42:37 +0200
• 70a7b0520a vhdl: only run encoders once all pixels are received Xiretza 2022-06-06 18:38:56 +0200
• 9ca64a7d4d Update ws2812 submodule Xiretza 2022-06-06 18:38:43 +0200
• 0f497e76e8 vhdl: implement bounds checking for strand number Xiretza 2022-06-06 18:25:27 +0200
• fcfa9eb7d0 vhdl: workaround ghdl#2080 Xiretza 2022-06-06 18:16:31 +0200
• 3c5c3a4555 vhdl: use big-endian network byte order Xiretza 2022-06-06 18:13:21 +0200
• 4bced13726 vhdl: implement magic number on receive Xiretza 2022-06-06 17:11:39 +0200
• 904f34f4d4 vhdl: implement frame number checking Xiretza 2022-06-06 16:45:16 +0200
• 4d07ec3fa1 vhdl: reorganize receive FSM to avoid ghdl issues Xiretza 2022-06-06 15:24:49 +0200
• 40caa85d92 vhdl: implement multiple strands Xiretza 2022-06-06 12:58:41 +0200
• 24e3b11588 Use little endian byte order in network streams Xiretza 2022-06-06 10:29:45 +0200
• ccd911dc1e vhdl: implement feedback packets Xiretza 2022-06-05 22:56:29 +0200
• d0e65a3126 vhdl: remove unused signals Xiretza 2022-06-05 22:26:24 +0200
• 79fce1afc1 vhdl: disable test UDP sender Xiretza 2022-06-05 21:35:50 +0200
• 9121ccfdbe vhdl: implement setting LEDs via UDP Xiretza 2022-06-05 21:34:31 +0200
• d5b0ee2cfa vhdl: rename NUM_DRIVERS to NUM_STRANDS Xiretza 2022-06-05 16:51:03 +0200
• 2ec250e79d vhdl: rename clk_sys to sys_clk Xiretza 2022-06-05 16:44:35 +0200
• 57e6daedcc vhdl: move ws2812 driver to splink module Xiretza 2022-06-05 16:42:26 +0200
• 94ff182aec Add README.md Xiretza 2022-06-05 16:36:06 +0200
• 01fe200d92 Pixel UDP port demo Xiretza 2022-06-05 16:35:20 +0200
• ba1aa9181e vhdl: add ws2812 demo Xiretza 2022-06-05 13:10:19 +0200
• ffbe87f1f1 Add ws2812 submodule Xiretza 2022-06-05 10:21:44 +0200
• de6a38044b vhdl: assert reset if PLL is not locked Xiretza 2022-06-04 21:53:14 +0200
• d624673804 Add liteeth core Xiretza 2022-06-04 21:46:16 +0200
• e7087eb7db makefile: switch to nextpnr toolchain Xiretza 2022-06-04 21:19:37 +0200
• 608c17d1a8 makefile: use relative paths Xiretza 2022-06-04 21:19:26 +0200
• 8257886f6b Add nextpnr-xilinx makefile Xiretza 2022-06-04 21:18:57 +0200
• 63557ba83f fix(Makefile.symbiflow): fix read_verilog yosys command Xiretza 2022-06-03 22:18:09 +0200
• eedf254b15 fix(gen_liteeth): fix configurations Xiretza 2022-06-03 22:17:13 +0200
• d6687786a7 Add basic tools and VHDL skeleton Xiretza 2022-06-03 19:11:07 +0200
• 5a9bb94922 Initial empty commit Xiretza 2022-05-11 18:15:30 +0200