vhdl: only run encoders once all pixels are received
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@ -40,6 +40,7 @@ architecture a of splink is
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signal current_frame: unsigned(31 downto 0);
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signal pixels_received: natural range 0 to MAX_STRAND_LEN-1;
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signal run : std_logic;
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signal clear_write_flags : std_logic;
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signal all_strands_written : std_logic;
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@ -69,6 +70,7 @@ begin
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port map (
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n_reset => not reset,
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clk => clk,
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run => run,
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led_addr => led_data_arr(i).addr,
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@ -119,10 +121,12 @@ begin
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begin
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if rising_edge(clk) then
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clear_write_flags <= '0';
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run <= '0';
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if all_strands_written then
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frame_number <= current_frame;
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clear_write_flags <= '1';
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run <= '1';
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end if;
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if reset then
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