vhdl: assert reset if PLL is not locked
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parent
d624673804
commit
de6a38044b
1 changed files with 10 additions and 2 deletions
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@ -131,6 +131,7 @@ architecture a of arty_a7 is
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end component PLLE2_BASE;
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signal pll_feedback : std_logic;
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signal pll_locked : std_logic;
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signal unbuf_clk_sys : std_logic;
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signal clk_sys : std_logic;
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@ -140,6 +141,8 @@ architecture a of arty_a7 is
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O : out std_logic
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);
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end component BUFG;
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signal sys_reset : std_logic;
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begin
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--leds_simple <= (others => '0');
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led0 <= (others => '0');
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@ -156,7 +159,8 @@ begin
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liteeth_inst: liteeth_core port map (
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sys_clock => clk_sys,
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sys_reset => '0',
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sys_reset => sys_reset,
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mii_eth_clocks_tx => mii_tx_clk,
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mii_eth_clocks_rx => mii_rx_clk,
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mii_eth_rst_n => mii_n_reset,
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@ -201,6 +205,8 @@ begin
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port map (
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RST => '0',
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PWRDWN => '0',
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LOCKED => pll_locked,
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CLKIN1 => clock_100mhz,
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CLKFBIN => pll_feedback,
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@ -216,13 +222,15 @@ begin
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O => clk_sys
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);
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sys_reset <= not pll_locked or not n_reset;
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splink: entity work.splink
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generic map (
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NUM_DRIVERS => NUM_DRIVERS
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)
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port map (
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clk => clk_sys,
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reset => not n_reset,
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reset => sys_reset,
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drivers => drivers
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);
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