vhdl: assert reset if PLL is not locked

This commit is contained in:
Xiretza 2022-06-04 21:53:14 +02:00
parent d624673804
commit de6a38044b

View file

@ -131,6 +131,7 @@ architecture a of arty_a7 is
end component PLLE2_BASE;
signal pll_feedback : std_logic;
signal pll_locked : std_logic;
signal unbuf_clk_sys : std_logic;
signal clk_sys : std_logic;
@ -140,6 +141,8 @@ architecture a of arty_a7 is
O : out std_logic
);
end component BUFG;
signal sys_reset : std_logic;
begin
--leds_simple <= (others => '0');
led0 <= (others => '0');
@ -156,7 +159,8 @@ begin
liteeth_inst: liteeth_core port map (
sys_clock => clk_sys,
sys_reset => '0',
sys_reset => sys_reset,
mii_eth_clocks_tx => mii_tx_clk,
mii_eth_clocks_rx => mii_rx_clk,
mii_eth_rst_n => mii_n_reset,
@ -201,6 +205,8 @@ begin
port map (
RST => '0',
PWRDWN => '0',
LOCKED => pll_locked,
CLKIN1 => clock_100mhz,
CLKFBIN => pll_feedback,
@ -216,13 +222,15 @@ begin
O => clk_sys
);
sys_reset <= not pll_locked or not n_reset;
splink: entity work.splink
generic map (
NUM_DRIVERS => NUM_DRIVERS
)
port map (
clk => clk_sys,
reset => not n_reset,
reset => sys_reset,
drivers => drivers
);