xiretza/splink
1
0
Fork 0
Code Issues Pull requests Projects Releases Wiki Activity

fix(gen_liteeth): fix configurations

Browse source
This commit is contained in:
Xiretza 2022-06-03 22:17:13 +02:00
parent d6687786a7
commit eedf254b15
1 changed files with 4 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
gen_liteeth.py
View file

@ -32,7 +32,7 @@ from liteeth.core import LiteEthUDPIPCore
# IOs ----------------------------------------------------------------------------------------------
MAC_ADDRESS = 0x00183e02a914
CLK_FREQ = int(125e6)
CLK_FREQ = int(100e6)
_io = [
# Clk / Rst
@ -148,11 +148,10 @@ class PHYCore(SoCMini):
)
# PHY --------------------------------------------------------------------------------------
phy = liteeth_phys.LiteEthPHYRMII
phy = liteeth_phys.LiteEthPHYMII
ethphy = phy(
refclk_cd=None,
clock_pads=platform.request("rmii_eth_clocks"),
pads=platform.request("rmii_eth")
clock_pads=platform.request("mii_eth_clocks"),
pads=platform.request("mii_eth")
)
self.submodules.ethphy = ethphy