vhdl: use big-endian network byte order
liteeth splits the rx data stream into 4-byte chunks and interprets them as little-endian 32-bit vecs; similar for the other direction.
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2 changed files with 27 additions and 2 deletions
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@ -2,6 +2,8 @@ library ieee;
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use ieee.std_logic_1164.all,
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ieee.numeric_std.all;
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use work.util.flip_endianness;
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entity arty_a7 is
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generic (
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IS_SIMULATION : std_logic := '0'
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@ -242,7 +244,7 @@ begin
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pixel_sink_last => pixel_sink_last,
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pixel_sink_last_be => pixel_sink_last_be,
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pixel_sink_ready => pixel_sink_ready,
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pixel_sink_data => pixel_sink_data,
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pixel_sink_data => flip_endianness(pixel_sink_data),
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-- source
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pixel_source_src_ip_address => pixel_source_src_ip_address,
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@ -337,7 +339,7 @@ begin
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udp_valid => pixel_source_valid,
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udp_last => pixel_source_last,
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udp_data => pixel_source_data,
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udp_data => flip_endianness(pixel_source_data),
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frame_number => frame_number,
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23
vhdl/util.vhdl
Normal file
23
vhdl/util.vhdl
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@ -0,0 +1,23 @@
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library ieee;
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use ieee.std_logic_1164.all;
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package util is
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function flip_endianness(val : in std_logic_vector) return std_logic_vector;
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end package;
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package body util is
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function flip_endianness(val : in std_logic_vector) return std_logic_vector is
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constant BYTES : natural := val'length / 8;
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variable ret : std_logic_vector(val'length-1 downto 0);
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begin
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assert val'length mod 8 = 0
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report "length of vector not a multiple of 8"
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severity failure;
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for i in 0 to BYTES-1 loop
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ret((BYTES-i)*8 - 1 downto (BYTES-i-1) * 8) := val((i+1)*8 - 1 downto i*8);
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end loop;
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return ret;
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end function;
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end package body;
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