vhdl: use big-endian network byte order

liteeth splits the rx data stream into 4-byte chunks and interprets them as
little-endian 32-bit vecs; similar for the other direction.
This commit is contained in:
Xiretza 2022-06-06 18:13:21 +02:00
parent 4bced13726
commit 3c5c3a4555
2 changed files with 27 additions and 2 deletions

View file

@ -2,6 +2,8 @@ library ieee;
use ieee.std_logic_1164.all,
ieee.numeric_std.all;
use work.util.flip_endianness;
entity arty_a7 is
generic (
IS_SIMULATION : std_logic := '0'
@ -242,7 +244,7 @@ begin
pixel_sink_last => pixel_sink_last,
pixel_sink_last_be => pixel_sink_last_be,
pixel_sink_ready => pixel_sink_ready,
pixel_sink_data => pixel_sink_data,
pixel_sink_data => flip_endianness(pixel_sink_data),
-- source
pixel_source_src_ip_address => pixel_source_src_ip_address,
@ -337,7 +339,7 @@ begin
udp_valid => pixel_source_valid,
udp_last => pixel_source_last,
udp_data => pixel_source_data,
udp_data => flip_endianness(pixel_source_data),
frame_number => frame_number,

23
vhdl/util.vhdl Normal file
View file

@ -0,0 +1,23 @@
library ieee;
use ieee.std_logic_1164.all;
package util is
function flip_endianness(val : in std_logic_vector) return std_logic_vector;
end package;
package body util is
function flip_endianness(val : in std_logic_vector) return std_logic_vector is
constant BYTES : natural := val'length / 8;
variable ret : std_logic_vector(val'length-1 downto 0);
begin
assert val'length mod 8 = 0
report "length of vector not a multiple of 8"
severity failure;
for i in 0 to BYTES-1 loop
ret((BYTES-i)*8 - 1 downto (BYTES-i-1) * 8) := val((i+1)*8 - 1 downto i*8);
end loop;
return ret;
end function;
end package body;