Add liteeth core

This commit is contained in:
Xiretza 2022-06-04 21:46:16 +02:00
parent e7087eb7db
commit d624673804
3 changed files with 160 additions and 10 deletions

View file

@ -222,4 +222,7 @@ set_property IOSTANDARD LVCMOS33 [get_ports {ck_dig_h[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ck_dig_h[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ck_dig_h[15]}]
create_clock -name clk_100mhz -period 10.000 [get_nets clock_100mhz]
create_clock -period 12.5 [get_nets clk_sys]
create_clock -period 40.0 [get_nets liteeth_inst.eth_rx_clk]
create_clock -period 40.0 [get_nets liteeth_inst.eth_tx_clk]

View file

@ -32,7 +32,7 @@ from liteeth.core import LiteEthUDPIPCore
# IOs ----------------------------------------------------------------------------------------------
MAC_ADDRESS = 0x00183e02a914
CLK_FREQ = int(100e6)
CLK_FREQ = int(80e6)
_io = [
# Clk / Rst

View file

@ -48,6 +48,98 @@ end arty_a7;
architecture a of arty_a7 is
constant NUM_DRIVERS: positive := 16;
signal drivers: std_logic_vector(NUM_DRIVERS-1 downto 0);
component liteeth_core is
port (
sys_clock : in std_logic;
sys_reset : in std_logic;
mii_eth_clocks_tx : in std_logic;
mii_eth_clocks_rx : in std_logic;
mii_eth_rst_n : out std_logic;
mii_eth_mdio : inout std_logic;
mii_eth_mdc : out std_logic;
mii_eth_rx_dv : in std_logic;
mii_eth_rx_er : in std_logic;
mii_eth_rx_data : in std_logic_vector(3 downto 0);
mii_eth_tx_en : out std_logic;
mii_eth_tx_data : out std_logic_vector(3 downto 0);
mii_eth_col : in std_logic;
mii_eth_crs : in std_logic;
ip_address : in std_logic_vector(31 downto 0);
dhcp_ip_address : in std_logic_vector(31 downto 0);
dhcp_sink_valid : in std_logic;
dhcp_sink_last : in std_logic;
dhcp_sink_ready : out std_logic;
dhcp_sink_data : in std_logic_vector(31 downto 0);
dhcp_source_valid : out std_logic;
dhcp_source_last : out std_logic;
dhcp_source_ready : in std_logic;
dhcp_source_data : out std_logic_vector(31 downto 0)
);
end component;
signal dhcp_source_valid : std_logic;
component PLLE2_BASE
generic (
CLKFBOUT_MULT : integer;
DIVCLK_DIVIDE : integer;
CLKIN1_PERIOD : real;
CLKOUT0_DIVIDE : integer := 0;
CLKOUT0_DUTY_CYCLE : real := 0.5;
CLKOUT0_PHASE : real := 0.0;
CLKOUT1_DIVIDE : integer := 0;
CLKOUT1_DUTY_CYCLE : real := 0.5;
CLKOUT1_PHASE : real := 0.0;
CLKOUT2_DIVIDE : integer := 0;
CLKOUT2_DUTY_CYCLE : real := 0.5;
CLKOUT2_PHASE : real := 0.0;
CLKOUT3_DIVIDE : integer := 0;
CLKOUT3_DUTY_CYCLE : real := 0.5;
CLKOUT3_PHASE : real := 0.0;
CLKOUT4_DIVIDE : integer := 0;
CLKOUT4_DUTY_CYCLE : real := 0.5;
CLKOUT4_PHASE : real := 0.0;
CLKOUT5_DIVIDE : integer := 0;
CLKOUT5_DUTY_CYCLE : real := 0.5;
CLKOUT5_PHASE : real := 0.0
);
port (
RST : in std_logic;
PWRDWN : in std_logic;
LOCKED : out std_logic;
CLKIN1 : in std_logic;
CLKFBIN : in std_logic;
CLKFBOUT : out std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic
);
end component PLLE2_BASE;
signal pll_feedback : std_logic;
signal unbuf_clk_sys : std_logic;
signal clk_sys : std_logic;
component BUFG
port (
I : in std_logic;
O : out std_logic
);
end component BUFG;
begin
--leds_simple <= (others => '0');
led0 <= (others => '0');
@ -57,24 +149,79 @@ begin
uart_tx <= '0';
mii_clk_25mhz <= '0';
mii_n_reset <= '0';
mii_mdio <= 'Z';
mii_mdc <= '0';
mii_tx_en <= '0';
mii_tx_data <= (others => '0');
ck_dig_l <= (others => 'Z');
ck_dig_h <= (others => 'Z');
leds_simple <= drivers(3 downto 0);
liteeth_inst: liteeth_core port map (
sys_clock => clk_sys,
sys_reset => '0',
mii_eth_clocks_tx => mii_tx_clk,
mii_eth_clocks_rx => mii_rx_clk,
mii_eth_rst_n => mii_n_reset,
mii_eth_mdio => mii_mdio,
mii_eth_mdc => mii_mdc,
mii_eth_rx_dv => mii_rx_dv,
mii_eth_rx_er => mii_rx_er,
mii_eth_rx_data => mii_rx_data,
mii_eth_tx_en => mii_tx_en,
mii_eth_tx_data => mii_tx_data,
mii_eth_col => mii_col,
mii_eth_crs => mii_crs,
ip_address => x"0a141e28", -- 10.20.30.40
dhcp_ip_address => x"0a141e29", -- 10.20.30.41
dhcp_sink_valid => '0',
dhcp_sink_last => '1',
dhcp_sink_data => x"cafebebe",
dhcp_source_valid => dhcp_source_valid,
dhcp_source_ready => '1'
);
-- 800 MHz VCO
-- 80 MHz system clock
-- 25 MHz MII clock
pll_inst: PLLE2_BASE
generic map (
CLKFBOUT_MULT => 8,
DIVCLK_DIVIDE => 1,
CLKIN1_PERIOD => 10.0,
CLKOUT0_DIVIDE => 10,
CLKOUT1_DIVIDE => 32,
CLKOUT2_DIVIDE => 10,
CLKOUT3_DIVIDE => 10,
CLKOUT4_DIVIDE => 10,
CLKOUT5_DIVIDE => 10
)
port map (
RST => '0',
PWRDWN => '0',
CLKIN1 => clock_100mhz,
CLKFBIN => pll_feedback,
CLKFBOUT => pll_feedback,
CLKOUT0 => unbuf_clk_sys,
CLKOUT1 => mii_clk_25mhz
);
bufg_clk_sys: BUFG
port map (
I => unbuf_clk_sys,
O => clk_sys
);
splink: entity work.splink
generic map (
NUM_DRIVERS => NUM_DRIVERS
)
port map (
clk => clock_100mhz,
clk => clk_sys,
reset => not n_reset,
drivers => drivers