parent
3c5c3a4555
commit
fcfa9eb7d0
1 changed files with 9 additions and 2 deletions
|
@ -194,6 +194,11 @@ architecture a of arty_a7 is
|
|||
|
||||
signal frame_number : unsigned(31 downto 0);
|
||||
signal prev_frame_number : unsigned(31 downto 0);
|
||||
|
||||
-- little-endian pixel sink data
|
||||
signal pixel_sink_data_le : std_logic_vector(31 downto 0);
|
||||
-- big-endian pixel source data
|
||||
signal pixel_source_data_be : std_logic_vector(31 downto 0);
|
||||
begin
|
||||
leds_simple <= (others => '0');
|
||||
led0 <= (others => '0');
|
||||
|
@ -244,7 +249,7 @@ begin
|
|||
pixel_sink_last => pixel_sink_last,
|
||||
pixel_sink_last_be => pixel_sink_last_be,
|
||||
pixel_sink_ready => pixel_sink_ready,
|
||||
pixel_sink_data => flip_endianness(pixel_sink_data),
|
||||
pixel_sink_data => pixel_sink_data_le,
|
||||
|
||||
-- source
|
||||
pixel_source_src_ip_address => pixel_source_src_ip_address,
|
||||
|
@ -257,6 +262,7 @@ begin
|
|||
pixel_source_ready => '1',
|
||||
pixel_source_data => pixel_source_data
|
||||
);
|
||||
pixel_sink_data_le <= flip_endianness(pixel_sink_data);
|
||||
|
||||
-- 800 MHz VCO
|
||||
-- 80 MHz system clock
|
||||
|
@ -339,10 +345,11 @@ begin
|
|||
|
||||
udp_valid => pixel_source_valid,
|
||||
udp_last => pixel_source_last,
|
||||
udp_data => flip_endianness(pixel_source_data),
|
||||
udp_data => pixel_source_data_be,
|
||||
|
||||
frame_number => frame_number,
|
||||
|
||||
drivers => drivers
|
||||
);
|
||||
pixel_source_data_be <= flip_endianness(pixel_source_data);
|
||||
end architecture;
|
||||
|
|
Loading…
Reference in a new issue