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vhdl: add ws2812 demo

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Xiretza 2022-06-05 13:10:19 +02:00
parent ffbe87f1f1
commit ba1aa9181e
1 changed files with 36 additions and 1 deletions
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37
vhdl/arty_a7.vhdl
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@ -19,7 +19,7 @@ entity arty_a7 is
pmod_a : in std_logic_vector(7 downto 0);
pmod_b : in std_logic_vector(7 downto 0);
pmod_c : in std_logic_vector(7 downto 0);
pmod_d : in std_logic_vector(7 downto 0);
pmod_d : out std_logic_vector(7 downto 0);
clock_100mhz : in std_logic;
@ -224,6 +224,41 @@ begin
sys_reset <= not pll_locked or not n_reset;
ws2812_inst: entity work.ws2812
generic map (
NUM_LEDS => 20,
COLOR_ORDER => "GRB",
T_CLK => 12.5 ns,
T0H => 0.35 us,
T0L => 0.8 us,
T1H => 0.7 us,
T1L => 0.6 us,
T_RES => 80 us
)
port map (
n_reset => not sys_reset,
clk => clk_sys,
led_addr => open,
led_red => x"ff",
led_green => x"00",
led_blue => x"ff",
dout => pmod_d(3)
);
-- https://github.com/YosysHQ/yosys/issues/3360
pmod_d(0) <= '0';
pmod_d(1) <= '0';
pmod_d(2) <= '0';
pmod_d(4) <= '0';
pmod_d(5) <= '0';
pmod_d(6) <= '0';
pmod_d(7) <= '0';
splink: entity work.splink
generic map (
NUM_DRIVERS => NUM_DRIVERS