vhdl: remove unused signals
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2 changed files with 3 additions and 20 deletions
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@ -119,11 +119,8 @@ architecture a of arty_a7 is
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signal pixel_source_src_ip_address : std_logic_vector(31 downto 0);
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signal pixel_source_src_port : std_logic_vector(15 downto 0);
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signal pixel_source_length : std_logic_vector(15 downto 0);
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signal pixel_source_valid : std_logic;
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signal pixel_source_last : std_logic;
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signal pixel_source_last_be : std_logic_vector(3 downto 0);
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signal pixel_source_ready : std_logic;
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signal pixel_source_data : std_logic_vector(31 downto 0);
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component PLLE2_BASE
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@ -245,11 +242,11 @@ begin
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pixel_source_src_ip_address => pixel_source_src_ip_address,
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pixel_source_src_port => pixel_source_src_port,
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pixel_source_length => pixel_source_length,
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pixel_source_length => open,
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pixel_source_valid => pixel_source_valid,
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pixel_source_last => pixel_source_last,
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pixel_source_last_be => pixel_source_last_be,
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pixel_source_ready => pixel_source_ready,
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pixel_source_last_be => open,
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pixel_source_ready => '1',
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pixel_source_data => pixel_source_data
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);
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@ -333,14 +330,8 @@ begin
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clk => sys_clk,
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reset => sys_reset,
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udp_src_ip_address => pixel_source_src_ip_address,
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udp_src_port => pixel_source_src_port,
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udp_length => pixel_source_length,
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udp_valid => pixel_source_valid,
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udp_last => pixel_source_last,
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udp_last_be => pixel_source_last_be,
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udp_ready => pixel_source_ready,
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udp_data => pixel_source_data,
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drivers => drivers
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@ -11,14 +11,8 @@ entity splink is
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clk : in std_logic;
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reset : in std_logic;
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udp_src_ip_address : in std_logic_vector(31 downto 0);
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udp_src_port : in std_logic_vector(15 downto 0);
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udp_length : in std_logic_vector(15 downto 0);
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udp_valid : in std_logic;
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udp_last : in std_logic;
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udp_last_be : in std_logic_vector(3 downto 0);
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udp_ready : out std_logic;
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udp_data : in std_logic_vector(31 downto 0);
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drivers : out std_logic_vector(NUM_STRANDS-1 downto 0)
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@ -82,6 +76,4 @@ begin
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end if;
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end if;
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end process;
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udp_ready <= '1';
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end architecture;
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