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VHDL 60%
Python 30.9%
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Xiretza eedf254b15 fix(gen_liteeth): fix configurations
2022-06-03 22:17:13 +02:00
vhdl Add basic tools and VHDL skeleton 2022-06-03 19:11:07 +02:00
.gitignore Add basic tools and VHDL skeleton 2022-06-03 19:11:07 +02:00
arty_a7_35.xdc Add basic tools and VHDL skeleton 2022-06-03 19:11:07 +02:00
gen_liteeth.py fix(gen_liteeth): fix configurations 2022-06-03 22:17:13 +02:00
Makefile Add basic tools and VHDL skeleton 2022-06-03 19:11:07 +02:00
Makefile.symbiflow Add basic tools and VHDL skeleton 2022-06-03 19:11:07 +02:00