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fix: reorganize outputs to 6 strands per PMOD

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This commit is contained in:
Xiretza 2022-07-14 14:17:55 +02:00
parent 99e52e611e
commit 77c602c8fd
1 changed files with 5 additions and 4 deletions
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9
vhdl/arty_a7.vhdl
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@ -36,7 +36,7 @@ entity arty_a7 is
-- when necessary
pmod_a : out std_logic_vector(7 downto 0);
pmod_b : out std_logic_vector(7 downto 0);
pmod_c : in std_logic_vector(7 downto 0);
pmod_c : out std_logic_vector(7 downto 0);
pmod_d : out std_logic_vector(7 downto 0);
clock_100mhz : in std_logic;
@ -320,9 +320,10 @@ begin
sys_reset <= not pll_locked or not n_reset;
pmod_a <= drivers(7 downto 0);
pmod_b <= drivers(15 downto 8);
pmod_d <= drivers(23 downto 16);
pmod_a <= "00" & drivers(5 downto 0);
pmod_b <= "00" & drivers(11 downto 6);
pmod_c <= "00" & drivers(17 downto 12);
pmod_d <= "00" & drivers(23 downto 18);
sender: process(sys_clk)
begin