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Xiretza 3c5c3a4555 vhdl: use big-endian network byte order 
liteeth splits the rx data stream into 4-byte chunks and interprets them as
little-endian 32-bit vecs; similar for the other direction.
2022-06-07 07:34:09 +02:00
vhdl vhdl: use big-endian network byte order 2022-06-07 07:34:09 +02:00
.gitignore Add basic tools and VHDL skeleton 2022-06-03 19:11:07 +02:00
.gitmodules Add ws2812 submodule 2022-06-05 10:21:44 +02:00
arty_a7_35.xdc vhdl: rename clk_sys to sys_clk 2022-06-05 21:36:10 +02:00
gen_liteeth.py Pixel UDP port demo 2022-06-05 16:35:20 +02:00
Makefile Add ws2812 submodule 2022-06-05 10:21:44 +02:00
Makefile.nextpnr Add nextpnr-xilinx makefile 2022-06-04 21:18:57 +02:00
Makefile.symbiflow fix(Makefile.symbiflow): fix read_verilog yosys command 2022-06-03 22:18:09 +02:00
README.md Add README.md 2022-06-05 16:36:06 +02:00

README.md

WS2812 driver gateware for blinkenwall v3

At 100 FPS, a single strand of WS2812 can only be just over 300 LEDs long:

MAX_LENGTH = (1 / FPS - RESET_TIME) / BIT_TIME / BITS_PER_PIXEL
318 = (1 / 100 - 50e-6) / 1.3e-6 / 24

Because blinkenwall v3 has 64 * 96 = 6144 pixels, driving it at 100 FPS requires at least 6144 / 318 = 20 parallel drivers. For simplicity, the wall is devided into 24 strands of 256 LEDs. Unfortunately, most microcontrollers have at most a couple WS2812-capable interfaces (typically SPI), so this would require coordinating several microcontrollers in parallel. A much more integrated solution is to instantiate as many WS2812 drivers as desired in an FPGA, then point the entire video firehose at the FPGA.