vhdl
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vhdl: assert reset if PLL is not locked
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2022-06-04 21:53:14 +02:00 |
.gitignore
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Add basic tools and VHDL skeleton
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2022-06-03 19:11:07 +02:00 |
arty_a7_35.xdc
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Add liteeth core
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2022-06-04 21:51:28 +02:00 |
gen_liteeth.py
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Add liteeth core
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2022-06-04 21:51:28 +02:00 |
Makefile
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makefile: switch to nextpnr toolchain
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2022-06-04 21:19:37 +02:00 |
Makefile.nextpnr
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Add nextpnr-xilinx makefile
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2022-06-04 21:18:57 +02:00 |