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10 commits 2 branches 0 tags 883 KiB
VHDL 60%
Python 30.9%
Makefile 9.1%
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Xiretza ffbe87f1f1 Add ws2812 submodule
2022-06-05 10:21:44 +02:00
vhdl Add ws2812 submodule 2022-06-05 10:21:44 +02:00
.gitignore Add basic tools and VHDL skeleton 2022-06-03 19:11:07 +02:00
.gitmodules Add ws2812 submodule 2022-06-05 10:21:44 +02:00
arty_a7_35.xdc Add liteeth core 2022-06-04 21:51:28 +02:00
gen_liteeth.py Add liteeth core 2022-06-04 21:51:28 +02:00
Makefile Add ws2812 submodule 2022-06-05 10:21:44 +02:00
Makefile.nextpnr Add nextpnr-xilinx makefile 2022-06-04 21:18:57 +02:00
Makefile.symbiflow fix(Makefile.symbiflow): fix read_verilog yosys command 2022-06-03 22:18:09 +02:00