vhdl: rename clk_sys to sys_clk
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57e6daedcc
commit
2ec250e79d
2 changed files with 11 additions and 11 deletions
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@ -222,7 +222,7 @@ set_property IOSTANDARD LVCMOS33 [get_ports {ck_dig_h[13]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {ck_dig_h[14]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {ck_dig_h[15]}]
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create_clock -period 12.5 [get_nets clk_sys]
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create_clock -period 12.5 [get_nets sys_clk]
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create_clock -period 40.0 [get_nets liteeth_inst.eth_rx_clk]
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create_clock -period 40.0 [get_nets liteeth_inst.eth_tx_clk]
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@ -168,8 +168,8 @@ architecture a of arty_a7 is
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signal pll_feedback : std_logic;
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signal pll_locked : std_logic;
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signal unbuf_clk_sys : std_logic;
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signal clk_sys : std_logic;
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signal unbuf_sys_clk : std_logic;
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signal sys_clk : std_logic;
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component BUFG
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port (
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@ -192,7 +192,7 @@ begin
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ck_dig_h <= (others => 'Z');
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liteeth_inst: liteeth_core port map (
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sys_clock => clk_sys,
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sys_clock => sys_clk,
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sys_reset => sys_reset,
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mii_eth_clocks_tx => mii_tx_clk,
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@ -270,14 +270,14 @@ begin
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CLKFBIN => pll_feedback,
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CLKFBOUT => pll_feedback,
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CLKOUT0 => unbuf_clk_sys,
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CLKOUT0 => unbuf_sys_clk,
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CLKOUT1 => mii_clk_25mhz
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);
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bufg_clk_sys: BUFG
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bufg_sys_clk: BUFG
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port map (
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I => unbuf_clk_sys,
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O => clk_sys
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I => unbuf_sys_clk,
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O => sys_clk
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);
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sys_reset <= not pll_locked or not n_reset;
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@ -286,14 +286,14 @@ begin
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pmod_b <= drivers(15 downto 8);
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pmod_d <= drivers(23 downto 16);
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sender: process(clk_sys)
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sender: process(sys_clk)
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constant COUNTER_MAX: natural := 80000000;
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variable counter: natural range 0 to COUNTER_MAX;
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constant NUM_WORDS: natural := 10;
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variable words_sent: natural range 0 to NUM_WORDS;
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begin
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if rising_edge(clk_sys) then
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if rising_edge(sys_clk) then
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if counter = COUNTER_MAX then
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pixel_sink_length <= std_logic_vector(to_unsigned(NUM_WORDS, 16));
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pixel_sink_data <= std_logic_vector(to_unsigned(16#30# + words_sent, 32));
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@ -320,7 +320,7 @@ begin
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NUM_DRIVERS => NUM_DRIVERS
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)
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port map (
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clk => clk_sys,
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clk => sys_clk,
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reset => sys_reset,
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drivers => drivers
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