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0f497e76e8
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vhdl: implement bounds checking for strand number
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2022-06-07 07:34:09 +02:00 |
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fcfa9eb7d0
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vhdl: workaround ghdl#2080
https://github.com/ghdl/ghdl/issues/2080
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2022-06-07 07:34:09 +02:00 |
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3c5c3a4555
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vhdl: use big-endian network byte order
liteeth splits the rx data stream into 4-byte chunks and interprets them as
little-endian 32-bit vecs; similar for the other direction.
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2022-06-07 07:34:09 +02:00 |
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4bced13726
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vhdl: implement magic number on receive
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2022-06-06 17:11:39 +02:00 |
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904f34f4d4
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vhdl: implement frame number checking
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2022-06-06 16:45:16 +02:00 |
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4d07ec3fa1
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vhdl: reorganize receive FSM to avoid ghdl issues
https://github.com/ghdl/ghdl/issues/2077
https://github.com/ghdl/ghdl/issues/2078
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2022-06-06 15:24:49 +02:00 |
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40caa85d92
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vhdl: implement multiple strands
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2022-06-06 12:58:41 +02:00 |
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24e3b11588
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Use little endian byte order in network streams
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2022-06-06 10:29:45 +02:00 |
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ccd911dc1e
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vhdl: implement feedback packets
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2022-06-05 22:56:29 +02:00 |
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d0e65a3126
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vhdl: remove unused signals
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2022-06-05 22:27:16 +02:00 |
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79fce1afc1
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vhdl: disable test UDP sender
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2022-06-05 21:36:10 +02:00 |
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9121ccfdbe
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vhdl: implement setting LEDs via UDP
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2022-06-05 21:36:10 +02:00 |
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d5b0ee2cfa
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vhdl: rename NUM_DRIVERS to NUM_STRANDS
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2022-06-05 21:36:10 +02:00 |
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2ec250e79d
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vhdl: rename clk_sys to sys_clk
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2022-06-05 21:36:10 +02:00 |
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57e6daedcc
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vhdl: move ws2812 driver to splink module
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2022-06-05 21:36:10 +02:00 |
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94ff182aec
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Add README.md
|
2022-06-05 16:36:06 +02:00 |
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01fe200d92
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Pixel UDP port demo
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2022-06-05 16:35:20 +02:00 |
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ba1aa9181e
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vhdl: add ws2812 demo
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2022-06-05 13:10:19 +02:00 |
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ffbe87f1f1
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Add ws2812 submodule
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2022-06-05 10:21:44 +02:00 |
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de6a38044b
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vhdl: assert reset if PLL is not locked
|
2022-06-04 21:53:14 +02:00 |
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d624673804
|
Add liteeth core
|
2022-06-04 21:51:28 +02:00 |
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e7087eb7db
|
makefile: switch to nextpnr toolchain
|
2022-06-04 21:19:37 +02:00 |
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608c17d1a8
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makefile: use relative paths
|
2022-06-04 21:19:26 +02:00 |
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8257886f6b
|
Add nextpnr-xilinx makefile
|
2022-06-04 21:18:57 +02:00 |
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63557ba83f
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fix(Makefile.symbiflow): fix read_verilog yosys command
|
2022-06-03 22:18:09 +02:00 |
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eedf254b15
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fix(gen_liteeth): fix configurations
|
2022-06-03 22:17:13 +02:00 |
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d6687786a7
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Add basic tools and VHDL skeleton
|
2022-06-03 19:11:07 +02:00 |
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5a9bb94922
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Initial empty commit
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2022-05-11 18:15:30 +02:00 |
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