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2ec250e79d
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vhdl: rename clk_sys to sys_clk
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2022-06-05 21:36:10 +02:00 |
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57e6daedcc
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vhdl: move ws2812 driver to splink module
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2022-06-05 21:36:10 +02:00 |
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94ff182aec
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Add README.md
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2022-06-05 16:36:06 +02:00 |
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01fe200d92
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Pixel UDP port demo
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2022-06-05 16:35:20 +02:00 |
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ba1aa9181e
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vhdl: add ws2812 demo
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2022-06-05 13:10:19 +02:00 |
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ffbe87f1f1
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Add ws2812 submodule
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2022-06-05 10:21:44 +02:00 |
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de6a38044b
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vhdl: assert reset if PLL is not locked
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2022-06-04 21:53:14 +02:00 |
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d624673804
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Add liteeth core
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2022-06-04 21:51:28 +02:00 |
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e7087eb7db
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makefile: switch to nextpnr toolchain
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2022-06-04 21:19:37 +02:00 |
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608c17d1a8
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makefile: use relative paths
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2022-06-04 21:19:26 +02:00 |
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8257886f6b
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Add nextpnr-xilinx makefile
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2022-06-04 21:18:57 +02:00 |
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63557ba83f
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fix(Makefile.symbiflow): fix read_verilog yosys command
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2022-06-03 22:18:09 +02:00 |
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eedf254b15
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fix(gen_liteeth): fix configurations
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2022-06-03 22:17:13 +02:00 |
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d6687786a7
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Add basic tools and VHDL skeleton
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2022-06-03 19:11:07 +02:00 |
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5a9bb94922
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Initial empty commit
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2022-05-11 18:15:30 +02:00 |
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