splink

Author	SHA1	Message	Date
Xiretza	e8476445b2	fix: use parallel ws2812 driver	2022-06-18 17:24:47 +02:00
Xiretza	645a838a73	vhdl: use UDP packet length	2022-06-07 07:34:09 +02:00
Xiretza	70a7b0520a	vhdl: only run encoders once all pixels are received	2022-06-07 07:34:09 +02:00
Xiretza	9ca64a7d4d	Update ws2812 submodule	2022-06-07 07:34:09 +02:00
Xiretza	0f497e76e8	vhdl: implement bounds checking for strand number	2022-06-07 07:34:09 +02:00
Xiretza	fcfa9eb7d0	vhdl: workaround ghdl#2080 https://github.com/ghdl/ghdl/issues/2080	2022-06-07 07:34:09 +02:00
Xiretza	3c5c3a4555	vhdl: use big-endian network byte order liteeth splits the rx data stream into 4-byte chunks and interprets them as little-endian 32-bit vecs; similar for the other direction.	2022-06-07 07:34:09 +02:00
Xiretza	4bced13726	vhdl: implement magic number on receive	2022-06-06 17:11:39 +02:00
Xiretza	904f34f4d4	vhdl: implement frame number checking	2022-06-06 16:45:16 +02:00
Xiretza	4d07ec3fa1	vhdl: reorganize receive FSM to avoid ghdl issues https://github.com/ghdl/ghdl/issues/2077 https://github.com/ghdl/ghdl/issues/2078	2022-06-06 15:24:49 +02:00
Xiretza	40caa85d92	vhdl: implement multiple strands	2022-06-06 12:58:41 +02:00
Xiretza	24e3b11588	Use little endian byte order in network streams	2022-06-06 10:29:45 +02:00
Xiretza	ccd911dc1e	vhdl: implement feedback packets	2022-06-05 22:56:29 +02:00
Xiretza	d0e65a3126	vhdl: remove unused signals	2022-06-05 22:27:16 +02:00
Xiretza	79fce1afc1	vhdl: disable test UDP sender	2022-06-05 21:36:10 +02:00
Xiretza	9121ccfdbe	vhdl: implement setting LEDs via UDP	2022-06-05 21:36:10 +02:00
Xiretza	d5b0ee2cfa	vhdl: rename NUM_DRIVERS to NUM_STRANDS	2022-06-05 21:36:10 +02:00
Xiretza	2ec250e79d	vhdl: rename clk_sys to sys_clk	2022-06-05 21:36:10 +02:00
Xiretza	57e6daedcc	vhdl: move ws2812 driver to splink module	2022-06-05 21:36:10 +02:00
Xiretza	01fe200d92	Pixel UDP port demo	2022-06-05 16:35:20 +02:00
Xiretza	ba1aa9181e	vhdl: add ws2812 demo	2022-06-05 13:10:19 +02:00
Xiretza	ffbe87f1f1	Add ws2812 submodule	2022-06-05 10:21:44 +02:00
Xiretza	de6a38044b	vhdl: assert reset if PLL is not locked	2022-06-04 21:53:14 +02:00
Xiretza	d624673804	Add liteeth core	2022-06-04 21:51:28 +02:00
Xiretza	d6687786a7	Add basic tools and VHDL skeleton	2022-06-03 19:11:07 +02:00

25 commits