Xiretza 3c5c3a4555 vhdl: use big-endian network byte order ... liteeth splits the rx data stream into 4-byte chunks and interprets them as little-endian 32-bit vecs; similar for the other direction.		2022-06-07 07:34:09 +02:00
..
ws2812_vhdl@0d1688f184	Add ws2812 submodule	2022-06-05 10:21:44 +02:00
arty_a7.vhdl	vhdl: use big-endian network byte order	2022-06-07 07:34:09 +02:00
splink.vhdl	vhdl: implement magic number on receive	2022-06-06 17:11:39 +02:00
util.vhdl	vhdl: use big-endian network byte order	2022-06-07 07:34:09 +02:00