 Xiretza
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5f589aca37
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Use wishbone interface for CPU port
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2022-07-14 16:05:49 +02:00 |
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Xiretza
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f026fcfe5c
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fix: workaround nextpnr-xilinx#42
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2022-07-14 15:59:32 +02:00 |
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Xiretza
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77c602c8fd
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fix: reorganize outputs to 6 strands per PMOD
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2022-07-14 15:59:32 +02:00 |
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Xiretza
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99e52e611e
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fix: add license
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2022-06-21 07:21:16 +02:00 |
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Xiretza
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645a838a73
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vhdl: use UDP packet length
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2022-06-07 07:34:09 +02:00 |
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Xiretza
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fcfa9eb7d0
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vhdl: workaround ghdl#2080
https://github.com/ghdl/ghdl/issues/2080
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2022-06-07 07:34:09 +02:00 |
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Xiretza
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3c5c3a4555
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vhdl: use big-endian network byte order
liteeth splits the rx data stream into 4-byte chunks and interprets them as
little-endian 32-bit vecs; similar for the other direction.
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2022-06-07 07:34:09 +02:00 |
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Xiretza
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904f34f4d4
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vhdl: implement frame number checking
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2022-06-06 16:45:16 +02:00 |
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Xiretza
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ccd911dc1e
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vhdl: implement feedback packets
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2022-06-05 22:56:29 +02:00 |
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Xiretza
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d0e65a3126
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vhdl: remove unused signals
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2022-06-05 22:27:16 +02:00 |
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Xiretza
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79fce1afc1
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vhdl: disable test UDP sender
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2022-06-05 21:36:10 +02:00 |
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Xiretza
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9121ccfdbe
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vhdl: implement setting LEDs via UDP
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2022-06-05 21:36:10 +02:00 |
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Xiretza
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d5b0ee2cfa
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vhdl: rename NUM_DRIVERS to NUM_STRANDS
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2022-06-05 21:36:10 +02:00 |
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Xiretza
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2ec250e79d
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vhdl: rename clk_sys to sys_clk
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2022-06-05 21:36:10 +02:00 |
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Xiretza
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57e6daedcc
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vhdl: move ws2812 driver to splink module
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2022-06-05 21:36:10 +02:00 |
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Xiretza
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01fe200d92
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Pixel UDP port demo
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2022-06-05 16:35:20 +02:00 |
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Xiretza
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ba1aa9181e
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vhdl: add ws2812 demo
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2022-06-05 13:10:19 +02:00 |
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Xiretza
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de6a38044b
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vhdl: assert reset if PLL is not locked
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2022-06-04 21:53:14 +02:00 |
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Xiretza
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d624673804
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Add liteeth core
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2022-06-04 21:51:28 +02:00 |
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Xiretza
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d6687786a7
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Add basic tools and VHDL skeleton
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2022-06-03 19:11:07 +02:00 |
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