83 lines
2 KiB
VHDL
83 lines
2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all,
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ieee.numeric_std.all;
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entity arty_a7 is
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generic (
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IS_SIMULATION : std_logic := '0'
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);
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port (
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n_reset : in std_logic;
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buttons : in std_logic_vector(3 downto 0);
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switches : in std_logic_vector(3 downto 0);
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leds_simple : out std_logic_vector(3 downto 0);
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led0, led1, led2, led3 : out std_logic_vector(2 downto 0);
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-- Pmod connectors - A+D standard, B+C high-speed.
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-- Defined as inputs by default for safety, change
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-- when necessary
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pmod_a : in std_logic_vector(7 downto 0);
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pmod_b : in std_logic_vector(7 downto 0);
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pmod_c : in std_logic_vector(7 downto 0);
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pmod_d : in std_logic_vector(7 downto 0);
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clock_100mhz : in std_logic;
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uart_rx : in std_logic;
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uart_tx : out std_logic;
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mii_clk_25mhz : out std_logic;
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mii_n_reset : out std_logic;
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mii_mdio : inout std_logic;
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mii_mdc : out std_logic;
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mii_rx_clk : in std_logic;
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mii_rx_er : in std_logic;
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mii_rx_dv : in std_logic;
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mii_rx_data : in std_logic_vector(3 downto 0);
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mii_tx_clk : in std_logic;
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mii_tx_en : out std_logic;
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mii_tx_data : out std_logic_vector(3 downto 0);
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mii_col : in std_logic;
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mii_crs : in std_logic;
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ck_dig_l : inout std_logic_vector(13 downto 0);
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ck_dig_h : inout std_logic_vector(41 downto 26)
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);
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end arty_a7;
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architecture a of arty_a7 is
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constant NUM_DRIVERS: positive := 16;
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signal drivers: std_logic_vector(NUM_DRIVERS-1 downto 0);
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begin
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--leds_simple <= (others => '0');
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led0 <= (others => '0');
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led1 <= (others => '0');
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led2 <= (others => '0');
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led3 <= (others => '0');
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uart_tx <= '0';
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mii_clk_25mhz <= '0';
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mii_n_reset <= '0';
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mii_mdio <= 'Z';
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mii_mdc <= '0';
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mii_tx_en <= '0';
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mii_tx_data <= (others => '0');
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ck_dig_l <= (others => 'Z');
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ck_dig_h <= (others => 'Z');
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leds_simple <= drivers(3 downto 0);
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splink: entity work.splink
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generic map (
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NUM_DRIVERS => NUM_DRIVERS
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)
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port map (
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clk => clock_100mhz,
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reset => not n_reset,
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drivers => drivers
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);
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end architecture;
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