389 lines
11 KiB
VHDL
389 lines
11 KiB
VHDL
-- splink, ethernet-connected LED controller
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-- Copyright (C) 2022 xiretza
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU Affero General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU Affero General Public License for more details.
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--
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-- You should have received a copy of the GNU Affero General Public License
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-- along with this program. If not, see <https://www.gnu.org/licenses/>.
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library ieee;
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use ieee.std_logic_1164.all,
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ieee.numeric_std.all;
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use work.util.flip_endianness;
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entity arty_a7 is
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generic (
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IS_SIMULATION : std_logic := '0'
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);
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port (
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n_reset : in std_logic;
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buttons : in std_logic_vector(3 downto 0);
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switches : in std_logic_vector(3 downto 0);
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leds_simple : out std_logic_vector(3 downto 0);
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led0, led1, led2, led3 : out std_logic_vector(2 downto 0);
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-- Pmod connectors - A+D standard, B+C high-speed.
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-- Defined as inputs by default for safety, change
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-- when necessary
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pmod_a : out std_logic_vector(7 downto 0);
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pmod_b : out std_logic_vector(7 downto 0);
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pmod_c : out std_logic_vector(7 downto 0);
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pmod_d : out std_logic_vector(7 downto 0);
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clock_100mhz : in std_logic;
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uart_rx : in std_logic;
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uart_tx : out std_logic;
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mii_clk_25mhz : out std_logic;
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mii_n_reset : out std_logic;
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mii_mdio : inout std_logic;
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mii_mdc : out std_logic;
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mii_rx_clk : in std_logic;
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mii_rx_er : in std_logic;
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mii_rx_dv : in std_logic;
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mii_rx_data : in std_logic_vector(3 downto 0);
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mii_tx_clk : in std_logic;
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mii_tx_en : out std_logic;
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mii_tx_data : out std_logic_vector(3 downto 0);
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mii_col : in std_logic;
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mii_crs : in std_logic;
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ck_dig_l : inout std_logic_vector(13 downto 0);
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ck_dig_h : inout std_logic_vector(41 downto 26)
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);
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end arty_a7;
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architecture a of arty_a7 is
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constant NUM_STRANDS: positive := 24;
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signal drivers: std_logic_vector(NUM_STRANDS-1 downto 0);
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component liteeth_core is
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port (
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sys_clock : in std_logic;
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sys_reset : in std_logic;
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mii_eth_clocks_tx : in std_logic;
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mii_eth_clocks_rx : in std_logic;
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mii_eth_rst_n : out std_logic;
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mii_eth_mdio : inout std_logic;
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mii_eth_mdc : out std_logic;
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mii_eth_rx_dv : in std_logic;
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mii_eth_rx_er : in std_logic;
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mii_eth_rx_data : in std_logic_vector(3 downto 0);
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mii_eth_tx_en : out std_logic;
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mii_eth_tx_data : out std_logic_vector(3 downto 0);
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mii_eth_col : in std_logic;
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mii_eth_crs : in std_logic;
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ip_address : in std_logic_vector(31 downto 0);
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--== WISHBONE PORT ==--
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wishbone_adr : in std_logic_vector(29 downto 0);
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wishbone_dat_w : in std_logic_vector(31 downto 0);
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wishbone_dat_r : out std_logic_vector(31 downto 0);
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wishbone_sel : in std_logic_vector(3 downto 0);
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wishbone_cyc : in std_logic;
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wishbone_stb : in std_logic;
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wishbone_ack : out std_logic;
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wishbone_we : in std_logic;
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wishbone_cti : in std_logic_vector(2 downto 0);
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wishbone_bte : in std_logic_vector(1 downto 0);
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wishbone_err : out std_logic;
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interrupt : out std_logic;
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--== PIXEL DATA PORT ==--
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pixel_bind_port : in std_logic_vector(15 downto 0);
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-- sink
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pixel_sink_dst_ip_address : in std_logic_vector(31 downto 0);
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pixel_sink_dst_port : in std_logic_vector(15 downto 0);
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pixel_sink_length : in std_logic_vector(15 downto 0);
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pixel_sink_valid : in std_logic;
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pixel_sink_last : in std_logic;
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pixel_sink_last_be : in std_logic_vector(3 downto 0);
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pixel_sink_ready : out std_logic;
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pixel_sink_data : in std_logic_vector(31 downto 0);
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-- source
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pixel_source_src_ip_address : out std_logic_vector(31 downto 0);
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pixel_source_src_port : out std_logic_vector(15 downto 0);
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pixel_source_length : out std_logic_vector(15 downto 0);
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pixel_source_valid : out std_logic;
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pixel_source_last : out std_logic;
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pixel_source_last_be : out std_logic_vector(3 downto 0);
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pixel_source_ready : in std_logic;
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pixel_source_data : out std_logic_vector(31 downto 0)
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);
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end component;
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signal pixel_sink_length : std_logic_vector(15 downto 0);
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signal pixel_sink_valid : std_logic;
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signal pixel_sink_last : std_logic;
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signal pixel_sink_last_be : std_logic_vector(3 downto 0);
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signal pixel_sink_ready : std_logic;
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signal pixel_sink_data : std_logic_vector(31 downto 0);
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signal pixel_source_src_ip_address : std_logic_vector(31 downto 0);
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signal pixel_source_src_port : std_logic_vector(15 downto 0);
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signal pixel_source_length : std_logic_vector(15 downto 0);
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signal pixel_source_valid : std_logic;
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signal pixel_source_last : std_logic;
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signal pixel_source_data : std_logic_vector(31 downto 0);
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signal remote_ip_address : std_logic_vector(31 downto 0);
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signal remote_port : std_logic_vector(15 downto 0);
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component PLLE2_BASE
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generic (
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CLKFBOUT_MULT : integer;
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DIVCLK_DIVIDE : integer;
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CLKIN1_PERIOD : real;
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CLKOUT0_DIVIDE : integer := 0;
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CLKOUT0_DUTY_CYCLE : real := 0.5;
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CLKOUT0_PHASE : real := 0.0;
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CLKOUT1_DIVIDE : integer := 0;
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CLKOUT1_DUTY_CYCLE : real := 0.5;
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CLKOUT1_PHASE : real := 0.0;
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CLKOUT2_DIVIDE : integer := 0;
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CLKOUT2_DUTY_CYCLE : real := 0.5;
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CLKOUT2_PHASE : real := 0.0;
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CLKOUT3_DIVIDE : integer := 0;
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CLKOUT3_DUTY_CYCLE : real := 0.5;
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CLKOUT3_PHASE : real := 0.0;
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CLKOUT4_DIVIDE : integer := 0;
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CLKOUT4_DUTY_CYCLE : real := 0.5;
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CLKOUT4_PHASE : real := 0.0;
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CLKOUT5_DIVIDE : integer := 0;
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CLKOUT5_DUTY_CYCLE : real := 0.5;
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CLKOUT5_PHASE : real := 0.0
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);
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port (
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RST : in std_logic;
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PWRDWN : in std_logic;
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LOCKED : out std_logic;
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CLKIN1 : in std_logic;
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CLKFBIN : in std_logic;
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CLKFBOUT : out std_logic;
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CLKOUT0 : out std_logic;
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CLKOUT1 : out std_logic;
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CLKOUT2 : out std_logic;
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CLKOUT3 : out std_logic;
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CLKOUT4 : out std_logic;
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CLKOUT5 : out std_logic
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);
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end component PLLE2_BASE;
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signal pll_feedback : std_logic;
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signal pll_locked : std_logic;
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signal unbuf_sys_clk : std_logic;
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signal sys_clk : std_logic;
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component BUFG
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port (
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I : in std_logic;
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O : out std_logic
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);
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end component BUFG;
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signal sys_reset : std_logic;
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signal frame_number : unsigned(31 downto 0);
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signal prev_frame_number : unsigned(31 downto 0);
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-- little-endian pixel sink data
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signal pixel_sink_data_le : std_logic_vector(31 downto 0);
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-- big-endian pixel source data
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signal pixel_source_data_be : std_logic_vector(31 downto 0);
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begin
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leds_simple <= (others => '0');
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led0 <= (others => '0');
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led1 <= (others => '0');
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led2 <= (others => '0');
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led3 <= (others => '0');
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uart_tx <= '0';
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ck_dig_l <= (others => 'Z');
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ck_dig_h <= (others => 'Z');
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liteeth_inst: liteeth_core port map (
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sys_clock => sys_clk,
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sys_reset => sys_reset,
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mii_eth_clocks_tx => mii_tx_clk,
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mii_eth_clocks_rx => mii_rx_clk,
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mii_eth_rst_n => mii_n_reset,
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mii_eth_mdio => mii_mdio,
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mii_eth_mdc => mii_mdc,
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mii_eth_rx_dv => mii_rx_dv,
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mii_eth_rx_er => mii_rx_er,
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mii_eth_rx_data => mii_rx_data,
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mii_eth_tx_en => mii_tx_en,
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mii_eth_tx_data => mii_tx_data,
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mii_eth_col => mii_col,
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mii_eth_crs => mii_crs,
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ip_address => x"0a141e28", -- 10.20.30.40
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--== WISHBONE PORT ==--
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wishbone_adr => (others => '1'),
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wishbone_dat_w => (others => '1'),
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wishbone_sel => (others => '1'),
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wishbone_cyc => '1',
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wishbone_stb => '1',
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wishbone_we => '1',
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wishbone_cti => (others => '1'),
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wishbone_bte => (others => '1'),
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--== PIXEL DATA PORT ==--
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pixel_bind_port => x"effd", -- port 61437 - "PIXEL"
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-- sink
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pixel_sink_dst_ip_address => remote_ip_address,
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pixel_sink_dst_port => remote_port,
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pixel_sink_length => pixel_sink_length,
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pixel_sink_valid => pixel_sink_valid,
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pixel_sink_last => pixel_sink_last,
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pixel_sink_last_be => pixel_sink_last_be,
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pixel_sink_ready => pixel_sink_ready,
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pixel_sink_data => pixel_sink_data_le,
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-- source
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pixel_source_src_ip_address => pixel_source_src_ip_address,
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pixel_source_src_port => pixel_source_src_port,
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pixel_source_length => pixel_source_length,
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pixel_source_valid => pixel_source_valid,
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pixel_source_last => pixel_source_last,
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pixel_source_last_be => open,
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pixel_source_ready => '1',
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pixel_source_data => pixel_source_data
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);
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pixel_sink_data_le <= flip_endianness(pixel_sink_data);
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-- 800 MHz VCO
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-- 80 MHz system clock
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-- 25 MHz MII clock
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pll_inst: PLLE2_BASE
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generic map (
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CLKFBOUT_MULT => 8,
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DIVCLK_DIVIDE => 1,
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CLKIN1_PERIOD => 10.0,
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CLKOUT0_DIVIDE => 10,
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CLKOUT1_DIVIDE => 32,
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CLKOUT2_DIVIDE => 10,
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CLKOUT3_DIVIDE => 10,
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CLKOUT4_DIVIDE => 10,
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CLKOUT5_DIVIDE => 10
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)
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port map (
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RST => '0',
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PWRDWN => '0',
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LOCKED => pll_locked,
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CLKIN1 => clock_100mhz,
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CLKFBIN => pll_feedback,
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CLKFBOUT => pll_feedback,
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CLKOUT0 => unbuf_sys_clk,
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CLKOUT1 => mii_clk_25mhz
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);
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bufg_sys_clk: BUFG
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port map (
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I => unbuf_sys_clk,
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O => sys_clk
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);
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sys_reset <= not pll_locked or not n_reset;
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pmod_a <= "00" & drivers(5 downto 0);
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pmod_b <= "00" & drivers(11 downto 6);
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pmod_c(7) <= '0';
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pmod_c(6) <= '0';
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pmod_c(5) <= drivers(17);
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pmod_c(4) <= drivers(16);
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pmod_c(3) <= drivers(15);
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pmod_c(2) <= drivers(14);
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-- workaround for https://github.com/gatecat/nextpnr-xilinx/issues/42#issuecomment-1183525828
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pmod_c(1) <= drivers(12);
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pmod_c(0) <= drivers(13);
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pmod_d <= "00" & drivers(23 downto 18);
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sender: process(sys_clk)
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begin
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if rising_edge(sys_clk) then
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if sys_reset then
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prev_frame_number <= frame_number;
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else
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if pixel_source_valid then
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remote_ip_address <= pixel_source_src_ip_address;
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remote_port <= pixel_source_src_port;
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end if;
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if frame_number /= prev_frame_number then
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prev_frame_number <= frame_number;
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pixel_sink_length <= x"0004";
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pixel_sink_data <= std_logic_vector(frame_number);
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pixel_sink_valid <= '1';
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pixel_sink_last <= '1';
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end if;
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if pixel_sink_ready and pixel_sink_valid then
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pixel_sink_valid <= '0';
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end if;
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end if;
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end if;
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end process;
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pixel_sink_last_be <= (pixel_sink_last, others => '0');
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splink: entity work.splink
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generic map (
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NUM_STRANDS => NUM_STRANDS
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)
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port map (
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clk => sys_clk,
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reset => sys_reset,
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udp_length => pixel_source_length,
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udp_valid => pixel_source_valid,
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udp_last => pixel_source_last,
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udp_data => pixel_source_data_be,
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frame_number => frame_number,
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drivers => drivers
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);
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pixel_source_data_be <= flip_endianness(pixel_source_data);
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end architecture;
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