xiretza
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  • Joined on 2018-10-02
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xiretza pushed to main at xiretza/splink_client 2022-06-17 22:01:19 +02:00
bbaa094f00 fix: remove unnecessary rename_all clap parameter
65381889ed feat: allow multiple animations
75d1b93f7e fix: cleanup main()
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xiretza pushed to main at xiretza/splink_client 2022-06-17 21:48:32 +02:00
43c53555d9 feat: allow smaller images
d89e34115f fix: rename bling animation
e383197483 feat: add image display mode
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xiretza pushed to main at xiretza/splink_client 2022-06-17 21:09:11 +02:00
cc29d5226b fix: rename bling animation
7020006e89 feat: add image display mode
8ab9cd7010 feat: add rainbow effect
0d8f11c712 feat: allow specifying strand subset
031245496e chore: formatting
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xiretza created branch main in xiretza/splink_client 2022-06-17 17:27:18 +02:00
xiretza pushed to main at xiretza/splink_client 2022-06-17 17:27:18 +02:00
893fcb8fb1 Initial commit
xiretza created repository xiretza/splink_client 2022-06-17 17:27:14 +02:00
xiretza pushed to master at IT-Syndikat/its-zones 2022-06-11 22:19:17 +02:00
70c3dc5735 Add etebase.it-syndikat.org record
xiretza pushed to main at xiretza/splink 2022-06-07 07:34:37 +02:00
6ff0e77d38 makefile: make ghdl error on warnings
645a838a73 vhdl: use UDP packet length
70a7b0520a vhdl: only run encoders once all pixels are received
9ca64a7d4d Update ws2812 submodule
0f497e76e8 vhdl: implement bounds checking for strand number
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xiretza pushed to main at xiretza/splink 2022-06-06 20:59:26 +02:00
0230edd2fb makefile: make ghdl error on warnings
2cc32eb4c2 vhdl: use UDP packet length
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xiretza pushed to main at xiretza/splink 2022-06-06 18:39:41 +02:00
ea8e6d4b49 vhdl: only run encoders once all pixels are received
62a06c6bcd Update ws2812 submodule
b97c708148 vhdl: implement bounds checking for strand number
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xiretza pushed to main at xiretza/splink 2022-06-06 18:18:34 +02:00
bad48d0e9b vhdl: workaround ghdl#2080
dc31375b55 vhdl: use big-endian network byte order
4bced13726 vhdl: implement magic number on receive
904f34f4d4 vhdl: implement frame number checking
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xiretza pushed to main at xiretza/splink 2022-06-06 15:29:19 +02:00
4d07ec3fa1 vhdl: reorganize receive FSM to avoid ghdl issues
40caa85d92 vhdl: implement multiple strands
24e3b11588 Use little endian byte order in network streams
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xiretza pushed to main at xiretza/splink 2022-06-05 22:56:43 +02:00
ccd911dc1e vhdl: implement feedback packets
d0e65a3126 vhdl: remove unused signals
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xiretza pushed to main at xiretza/splink 2022-06-05 21:36:16 +02:00
79fce1afc1 vhdl: disable test UDP sender
9121ccfdbe vhdl: implement setting LEDs via UDP
d5b0ee2cfa vhdl: rename NUM_DRIVERS to NUM_STRANDS
2ec250e79d vhdl: rename clk_sys to sys_clk
57e6daedcc vhdl: move ws2812 driver to splink module
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xiretza pushed to main at xiretza/splink 2022-06-05 13:10:30 +02:00
ba1aa9181e vhdl: add ws2812 demo
xiretza pushed to main at xiretza/splink 2022-06-05 10:22:23 +02:00
ffbe87f1f1 Add ws2812 submodule
xiretza pushed to main at xiretza/splink 2022-06-04 21:53:57 +02:00
de6a38044b vhdl: assert reset if PLL is not locked
xiretza pushed to main at xiretza/splink 2022-06-04 21:51:37 +02:00
d624673804 Add liteeth core
xiretza pushed to main at xiretza/splink 2022-06-04 21:46:26 +02:00
e2b658269d Add liteeth core
xiretza pushed to main at xiretza/splink 2022-06-04 21:20:24 +02:00
e7087eb7db makefile: switch to nextpnr toolchain
608c17d1a8 makefile: use relative paths
8257886f6b Add nextpnr-xilinx makefile
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