xiretza/splink
1
0
Fork 0
Code Issues Pull requests Projects Releases Wiki Activity

Compare commits

base: xiretza:63557ba83fddeaf7b210c85532df248447da873e
Branches Tags
xiretza:main
xiretza:liteeth-wishbone
...
compare: xiretza:e7087eb7db830fd9d1029dd71169ccaae04c7260
Branches Tags
xiretza:liteeth-wishbone
xiretza:main

3 commits
63557ba83f ... e7087eb7db

Author SHA1 Message Date
Xiretza e7087eb7db makefile: switch to nextpnr toolchain 2022-06-04 21:19:37 +02:00
Xiretza 608c17d1a8 makefile: use relative paths 2022-06-04 21:19:26 +02:00
Xiretza 8257886f6b Add nextpnr-xilinx makefile 2022-06-04 21:18:57 +02:00
2 changed files with 17 additions and 3 deletions
Show stats Expand all files Collapse all files

6
Makefile
View file

@ -1,8 +1,8 @@
.SECONDARY:
SYNTH_TOOLCHAIN ?= symbiflow
SYNTH_TOOLCHAIN ?= nextpnr
WORKDIR = $(PWD)/work
WORKDIR = work
GHDL_WORKDIR = $(WORKDIR)/ghdl
SYMBIYOSYS_WORKDIR = $(WORKDIR)/symbiyosys
LITEX_WORKDIR = $(WORKDIR)/litex
@ -30,7 +30,7 @@ GTKWAVE = gtkwave
# synthesis
XDC = $(PWD)/arty_a7_35.xdc
XDC = arty_a7_35.xdc
PART = xc7a35tcsg324-1

14
Makefile.nextpnr Normal file
View file

@ -0,0 +1,14 @@
SYNTH_OUTPUT_FILE = $(SYNTH_WORKDIR)/$(YOSYS_MODULE_NAME).json
$(SYNTH_WORKDIR)/%.json: $(VHDL_FILES) $(VERILOG_FILES) | $(SYNTH_WORKDIR) $(GHDL_WORKDIR)/work-obj$(VHDL_STD).cf
$(GHDL) make $(GHDL_FLAGS) $(SYNTH_ENTITY)
$(YOSYS) -m $(GHDL_YOSYS_PLUGIN) -l $(SYNTH_WORKDIR)/yosys.log -p 'ghdl $(GHDL_FLAGS) $(SYNTH_ENTITY); read_verilog $(VERILOG_FILES); chformal -remove; synth_xilinx -nodsp -nosrl -flatten -top $*; write_json $@'
$(SYNTH_WORKDIR)/%.fasm: $(SYNTH_WORKDIR)/%.json $(XDC)
$(NEXTPNR) --xdc $(XDC) --json $< --chipdb /usr/share/nextpnr/xilinx-chipdb/$(PART).bin --fasm $@
$(SYNTH_WORKDIR)/%.frames: $(SYNTH_WORKDIR)/%.fasm
$(FASM2FRAMES) --db-root $(XRAY_DATABASE) --part $(PART) $< $@
$(SYNTH_WORKDIR)/%.bit: $(SYNTH_WORKDIR)/%.frames $(XRAY_DATABASE)/$(PART)/part.yaml
$(FRAMES2BIT) --part-file $(XRAY_DATABASE)/$(PART)/part.yaml --part-name $(PART) --frm-file $< --output-file $@