vhdl: only run encoders once all pixels are received

vhdl/splink.vhdl

@@ -40,6 +40,7 @@ architecture a of splink is
 	signal current_frame: unsigned(31 downto 0);
 	signal pixels_received: natural range 0 to MAX_STRAND_LEN-1;
 
+	signal run : std_logic;
 	signal clear_write_flags : std_logic;
 
 	signal all_strands_written : std_logic;
@@ -69,6 +70,7 @@ begin
 			port map (
 				n_reset => not reset,
 				clk     => clk,
+				run     => run,
 
 				led_addr => led_data_arr(i).addr,
 
@@ -119,10 +121,12 @@ begin
 	begin
 		if rising_edge(clk) then
 			clear_write_flags <= '0';
+			run <= '0';
 
 			if all_strands_written then
 				frame_number <= current_frame;
 				clear_write_flags <= '1';
+				run <= '1';
 			end if;
 
 			if reset then
@@ -146,10 +150,12 @@ begin
 						-- TODO udp_length, range check with MAX_STRAND_LEN
 						num_pixels <= MAX_STRAND_LEN;
 
-						-- FIXME bounds check
-						active_strand <= to_integer(unsigned(udp_data));
-
-						receive_state <= FRAME_NUM;
+						if unsigned(udp_data) >= NUM_STRANDS then
+							receive_state <= DROP;
+						else
+							active_strand <= to_integer(unsigned(udp_data));
+							receive_state <= FRAME_NUM;
+						end if;
 
 					when FRAME_NUM =>
 						if not some_strands_written then

vhdl/ws2812_vhdl

@@ -1 +1 @@
-Subproject commit 0d1688f1840b8b5894b9f4cd027fcc1653dd3657
+Subproject commit 0d4146d3a3abeb6a20f9228e61e58f95a71b340a