makefile: make ghdl error on warnings

https://github.com/ghdl/ghdl/issues/2080

Makefile.nextpnr

@@ -2,7 +2,7 @@ SYNTH_OUTPUT_FILE = $(SYNTH_WORKDIR)/$(YOSYS_MODULE_NAME).json
 
 $(SYNTH_WORKDIR)/%.json: $(VHDL_FILES) $(VERILOG_FILES) | $(SYNTH_WORKDIR) $(GHDL_WORKDIR)/work-obj$(VHDL_STD).cf
 	$(GHDL) make $(GHDL_FLAGS) $(SYNTH_ENTITY)
-	$(YOSYS) -m $(GHDL_YOSYS_PLUGIN) -l $(SYNTH_WORKDIR)/yosys.log -p 'ghdl $(GHDL_FLAGS) $(SYNTH_ENTITY); read_verilog $(VERILOG_FILES); chformal -remove; synth_xilinx -nodsp -nosrl -flatten -top $*; write_json $@'
+	$(YOSYS) -m $(GHDL_YOSYS_PLUGIN) -l $(SYNTH_WORKDIR)/yosys.log -p 'ghdl $(GHDL_FLAGS) -Werror -Wno-error=binding $(SYNTH_ENTITY); read_verilog $(VERILOG_FILES); chformal -remove; synth_xilinx -nodsp -nosrl -flatten -top $*; write_json $@'
 
 $(SYNTH_WORKDIR)/%.fasm: $(SYNTH_WORKDIR)/%.json $(XDC)
 	$(NEXTPNR) --xdc $(XDC) --json $< --chipdb /usr/share/nextpnr/xilinx-chipdb/$(PART).bin --fasm $@

vhdl/arty_a7.vhdl

@@ -2,6 +2,8 @@ library ieee;
 use ieee.std_logic_1164.all,
     ieee.numeric_std.all;
 
+use work.util.flip_endianness;
+
 entity arty_a7 is
 	generic (
 		IS_SIMULATION : std_logic := '0'
@@ -119,6 +121,7 @@ architecture a of arty_a7 is
 	signal pixel_source_src_ip_address : std_logic_vector(31 downto 0);
 	signal pixel_source_src_port : std_logic_vector(15 downto 0);
 
+	signal pixel_source_length : std_logic_vector(15 downto 0);
 	signal pixel_source_valid : std_logic;
 	signal pixel_source_last : std_logic;
 	signal pixel_source_data : std_logic_vector(31 downto 0);
@@ -192,6 +195,11 @@ architecture a of arty_a7 is
 
 	signal frame_number : unsigned(31 downto 0);
 	signal prev_frame_number : unsigned(31 downto 0);
+
+	-- little-endian pixel sink data
+	signal pixel_sink_data_le : std_logic_vector(31 downto 0);
+	-- big-endian pixel source data
+	signal pixel_source_data_be : std_logic_vector(31 downto 0);
 begin
 	leds_simple <= (others => '0');
 	led0 <= (others => '0');
@@ -242,19 +250,20 @@ begin
 		pixel_sink_last => pixel_sink_last,
 		pixel_sink_last_be => pixel_sink_last_be,
 		pixel_sink_ready => pixel_sink_ready,
-		pixel_sink_data => pixel_sink_data,
+		pixel_sink_data => pixel_sink_data_le,
 
 		-- source
 		pixel_source_src_ip_address => pixel_source_src_ip_address,
 		pixel_source_src_port => pixel_source_src_port,
 
-		pixel_source_length => open,
+		pixel_source_length => pixel_source_length,
 		pixel_source_valid => pixel_source_valid,
 		pixel_source_last => pixel_source_last,
 		pixel_source_last_be => open,
 		pixel_source_ready => '1',
 		pixel_source_data => pixel_source_data
 	);
+	pixel_sink_data_le <= flip_endianness(pixel_sink_data);
 
 	-- 800 MHz VCO
 	-- 80 MHz system clock
@@ -335,12 +344,14 @@ begin
 			clk => sys_clk,
 			reset => sys_reset,
 
+			udp_length => pixel_source_length,
 			udp_valid => pixel_source_valid,
 			udp_last => pixel_source_last,
-			udp_data => pixel_source_data,
+			udp_data => pixel_source_data_be,
 
 			frame_number => frame_number,
 
 			drivers => drivers
 		);
+	pixel_source_data_be <= flip_endianness(pixel_source_data);
 end architecture;

vhdl/splink.vhdl

@@ -11,6 +11,7 @@ entity splink is
 		clk : in std_logic;
 		reset : in std_logic;
 
+		udp_length : in std_logic_vector(15 downto 0);
 		udp_valid : in std_logic;
 		udp_last : in std_logic;
 		udp_data : in std_logic_vector(31 downto 0);
@@ -40,6 +41,7 @@ architecture a of splink is
 	signal current_frame: unsigned(31 downto 0);
 	signal pixels_received: natural range 0 to MAX_STRAND_LEN-1;
 
+	signal run : std_logic;
 	signal clear_write_flags : std_logic;
 
 	signal all_strands_written : std_logic;
@@ -47,6 +49,8 @@ architecture a of splink is
 
 	-- "PIXL"
 	constant MAGIC_NUMBER : std_logic_vector(31 downto 0) := x"5049584c";
+	-- magic + frame num + strand num (4 bytes each)
+	constant HEADER_LEN : natural := 12;
 
 	type receive_state_t is (MAGIC, FRAME_NUM, STRAND_NUM, DATA, DROP);
 	constant RESET_STATE : receive_state_t := MAGIC;
@@ -69,6 +73,7 @@ begin
 			port map (
 				n_reset => not reset,
 				clk     => clk,
+				run     => run,
 
 				led_addr => led_data_arr(i).addr,
 
@@ -119,10 +124,12 @@ begin
 	begin
 		if rising_edge(clk) then
 			clear_write_flags <= '0';
+			run <= '0';
 
 			if all_strands_written then
 				frame_number <= current_frame;
 				clear_write_flags <= '1';
+				run <= '1';
 			end if;
 
 			if reset then
@@ -136,20 +143,24 @@ begin
 
 				case receive_state is
 					when MAGIC =>
-						if udp_data = MAGIC_NUMBER then
-							receive_state <= STRAND_NUM;
-						else
+						if udp_data /= MAGIC_NUMBER then
 							receive_state <= DROP;
+						else
+							if (unsigned(udp_length) - HEADER_LEN) / 4 > MAX_STRAND_LEN then
+								receive_state <= DROP;
+							else
+								num_pixels <= (to_integer(unsigned(udp_length)) - HEADER_LEN) / 4;
+								receive_state <= STRAND_NUM;
+							end if;
 						end if;
 
 					when STRAND_NUM =>
-						-- TODO udp_length, range check with MAX_STRAND_LEN
-						num_pixels <= MAX_STRAND_LEN;
-
-						-- FIXME bounds check
-						active_strand <= to_integer(unsigned(udp_data));
-
-						receive_state <= FRAME_NUM;
+						if unsigned(udp_data) >= NUM_STRANDS then
+							receive_state <= DROP;
+						else
+							active_strand <= to_integer(unsigned(udp_data));
+							receive_state <= FRAME_NUM;
+						end if;
 
 					when FRAME_NUM =>
 						if not some_strands_written then

vhdl/util.vhdl

@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package util is
+	function flip_endianness(val : in std_logic_vector) return std_logic_vector;
+end package;
+
+package body util is
+	function flip_endianness(val : in std_logic_vector) return std_logic_vector is
+		constant BYTES : natural := val'length / 8;
+		variable ret : std_logic_vector(val'length-1 downto 0);
+	begin
+		assert val'length mod 8 = 0
+			report "length of vector not a multiple of 8"
+			severity failure;
+
+		for i in 0 to BYTES-1 loop
+			ret((BYTES-i)*8 - 1 downto (BYTES-i-1) * 8) := val((i+1)*8 - 1 downto i*8);
+		end loop;
+
+		return ret;
+	end function;
+end package body;

vhdl/ws2812_vhdl

@@ -1 +1 @@
-Subproject commit 0d1688f1840b8b5894b9f4cd027fcc1653dd3657
+Subproject commit 0d4146d3a3abeb6a20f9228e61e58f95a71b340a