|
637573fd43
|
Update core diagram
|
2020-03-30 23:38:10 +02:00 |
|
|
c15a3ec470
|
Improve phrasing
|
2020-03-30 20:56:18 +02:00 |
|
|
3e66e5d6c8
|
Add info about external bus clock speed
|
2020-03-30 20:55:43 +02:00 |
|
|
e86df5b9ba
|
Link to VHDL intro appendix
|
2020-03-30 20:54:36 +02:00 |
|
|
59299f196c
|
Cite VHDL's strong typing
|
2020-03-30 20:54:17 +02:00 |
|
|
1eaddf7d3d
|
Rework heading hierarchy
|
2020-03-30 15:20:53 +02:00 |
|
|
103a8e3d19
|
Turn VHDL introduction into appendix
|
2020-03-30 15:18:16 +02:00 |
|
|
3dc6bbf390
|
Misc fixes and improvements
|
2020-03-29 22:01:05 +02:00 |
|
|
ffb1fe4060
|
Add citations for GitLab CI and RISC-V spec
|
2020-03-29 21:58:14 +02:00 |
|
|
254a064680
|
Check all citation links and add urldate=
|
2020-03-29 21:57:24 +02:00 |
|
|
3b65229eae
|
Add information about formal verification
|
2020-03-29 19:03:49 +02:00 |
|
|
e891568008
|
Small fixes
|
2020-03-29 18:05:21 +02:00 |
|
|
40bc2327fd
|
Add information about DRAM interface
|
2020-03-29 18:05:05 +02:00 |
|
|
89f0a1565e
|
Improve FPGA comparison tables
|
2020-03-29 18:04:34 +02:00 |
|
|
239106c2fd
|
Add nbsp before citations
|
2020-03-29 18:03:16 +02:00 |
|
|
dc77d4bf61
|
Add labels and captions to listings
|
2020-03-27 14:20:22 +01:00 |
|
|
ad723217ad
|
Add information about external bus
|
2020-03-27 12:50:24 +01:00 |
|
|
244380ee5f
|
Fix citations, change citation style
|
2020-03-27 12:49:50 +01:00 |
|
|
e65030ef47
|
Add information about riscv compliance tests
|
2020-03-27 12:49:38 +01:00 |
|
|
ed378c0917
|
Merge batman content
|
2020-03-23 14:02:38 +01:00 |
|
|
1cb525748f
|
Fix compilation, add gitignore
|
2020-03-23 13:20:25 +01:00 |
|
|
bf239165f8
|
Cite more sources, use figures for graphics
|
2020-03-21 14:35:11 +01:00 |
|
|
52f3c6b0a7
|
Add information about ws2812 driver
|
2020-03-21 14:27:34 +01:00 |
|
|
e685cdea10
|
Fix Eater CPU publication year in bibliography
|
2020-03-20 10:19:31 +01:00 |
|
|
279e78331b
|
Update Hello World example, demonstrate synthesis
|
2020-03-20 10:16:40 +01:00 |
|
|
c4a71b39dd
|
Misc updates, add core and SoC docs
|
2020-03-01 17:13:51 +01:00 |
|
|
9d04e5ca2b
|
Update gitignore
|
2020-02-28 18:35:54 +01:00 |
|
|
ae4c533320
|
Add bibliography
|
2020-02-28 18:35:10 +01:00 |
|
|
38e12fa78b
|
Add Makefile and VHDL headers generation
|
2020-02-28 11:21:08 +01:00 |
|
|
387e9d61c6
|
Add initial outline of DS
|
2019-12-10 15:32:02 +01:00 |
|
|
3b360e3237
|
Move sample DS
|
2019-12-10 14:23:44 +01:00 |
|
|
b9fa071e76
|
Initial import
|
2019-09-20 17:32:06 +02:00 |
|
|
35b62c8251
|
Adeed tex files for dipl
Signed-off-by: Tyrolyean <tyrolyean@tyrolyean.net>
|
2019-09-07 18:15:15 +02:00 |
|
|
bb9d39a95d
|
Added correction and corrected version
as given by the allmighty XH. All behail him!
Signed-off-by: Tyrolyean <tyrolyean@tyrolyean.net>
|
2019-07-01 23:41:19 +02:00 |
|
|
6e711be18f
|
Added initial antrag
Signed-off-by: Tyrolyean <tyrolyean@tyrolyean.net>
|
2019-07-01 23:40:11 +02:00 |
|
|
b7fae59d8e
|
INITIAL COMMIT
Signed-off-by: Tyrolyean <tyrolyean@tyrolyean.net>
|
2019-07-01 23:38:26 +02:00 |
|