Our diploma thesis

Xiretza 38e12fa78b Add Makefile and VHDL headers generation		2020-02-28 11:21:08 +01:00
pics	Initial import	2019-09-20 17:32:06 +02:00
vhdl_intro	Add initial outline of DS	2019-12-10 15:32:02 +01:00
.gitignore	Add initial outline of DS	2019-12-10 15:32:02 +01:00
Diplomschrift.tex	Add initial outline of DS	2019-12-10 15:32:02 +01:00
Diplomschrift_original.tex	Move sample DS	2019-12-10 14:23:44 +01:00
generate_entity_headers.py	Add Makefile and VHDL headers generation	2020-02-28 11:21:08 +01:00
Makefile	Add Makefile and VHDL headers generation	2020-02-28 11:21:08 +01:00
preamble.tex	Add initial outline of DS	2019-12-10 15:32:02 +01:00