Cite more sources, use figures for graphics

Diplomschrift.bib

@@ -11,13 +11,49 @@
     year   = {2016},
 }
 
-@unpublished{yosys,
+@unpublished{yosys-paper,
     author = {Clifford Wolf, Johann Glaser},
     title  = {Yosys - A Free Verilog Synthesis Suite},
     url    = {http://www.clifford.at/yosys/files/yosys-austrochip2013.pdf},
     year   = {2013},
 }
 
+@software{yosys,
+    author = {Various Contributors},
+    title  = {Yosys - Yosys Open SYnthesis Suite},
+    url    = {https://github.com/YosysHQ/yosys},
+}
+
+@software{nextpnr,
+    author = {Various Contributors},
+    title  = {nextpnr - a portable FPGA place and route tool},
+    url    = {https://github.com/YosysHQ/nextpnr},
+}
+
+@software{nextpnr-xilinx,
+    author = {David Shah},
+    title  = {nextpnr-xilinx},
+    url    = {https://github.com/daveshah1/nextpnr-xilinx},
+}
+
+@online{prjxray,
+    author = {SymbiFlow},
+    title  = {Project X-Ray},
+    url    = {https://github.com/SymbiFlow/prjxray},
+}
+
+@software{ghdlsynth-beta,
+    author = {Tristan Gingold},
+    title  = {ghdlsynth-beta},
+    url    = {https://github.com/tgingold/ghdlsynth-beta},
+}
+
+@software{ghdl,
+    author = {Tristan Gingold},
+    title  = {ghdl},
+    url    = {https://github.com/ghdl/ghdl},
+}
+
 @software{liteeth,
     author = {Florent Kermarrec},
     title  = {LiteEth},

core/core.tex

@@ -18,7 +18,11 @@ It is constructed according to the traditional RISC pipeline:
 
 \section{Overview}
 
-\includegraphics[width=\textwidth]{core_diagram.png}
+\begin{figure}
+%\includegraphics[width=\textwidth]{core_diagram.png}
+% TODO
+\caption{Block diagram of the CPU core}
+\end{figure}
 
 \section{Control}
 

soc/soc.tex

@@ -52,11 +52,11 @@ Vendor tools are usually free-of-charge for basic usage, but this also means the
 
 \subsection{Free Software Tools}
 
-A somewhat recent development is the creation of Free Software\footnotemark FPGA toolchains. A breakthrough was achieved by Claire (formerly Clifford) Wolf in 2013 with yosys\cite{yosys}, a feature-complete Verilog synthesis suite for Lattice's \texttt{iCE40} FPGA series.
+A somewhat recent development is the creation of Free Software\footnotemark{} FPGA toolchains. A breakthrough was achieved by Claire (formerly Clifford) Wolf in 2013 with yosys\cite{yosys-paper, yosys}, a feature-complete Verilog synthesis suite for Lattice's \texttt{iCE40} FPGA series.
     \footnotetext{``Free Software'' refers to software that grants its user the freedom to share, study and modify it - see \url{https://www.fsf.org/about/what-is-free-software}.}
-Since then, both yosys and place-and-route tools like nextpnr\footnote{\url{https://github.com/YosysHQ/nextpnr}} have matured, however Lattice's iCE40 and ECP5 remained the only supported FPGA architectures for place-and-route.
+Since then, both yosys and place-and-route tools like nextpnr\cite{nextpnr} have matured, however Lattice's iCE40 and ECP5 remained the only supported FPGA architectures for place-and-route.
 
-Thus, two obstacles remained for Free toolchains to be viable for this project: synthesizing from VHDL code and synthesizing to Artix-7 FPGAs. During the development of the project, both of these were solved: Tristan Gingold released \texttt{ghdlsynth-beta}\footnote{\url{https://github.com/tgingold/ghdlsynth-beta}}, a bridge between GHDL and yosys allowing VHDL to be synthesized just the same as Verilog, and Dave Shah added Xilinx support to nextpnr. The latter was preceded by many months of volunteer work reverse-engineering the Xilinx bitstream format as part of \textit{Project X-Ray}\footnote{\url{https://symbiflow.github.io/prjxray-db/}}.
+Thus, two obstacles remained for Free toolchains to be viable for this project: synthesizing \emph{from} VHDL code and synthesizing \emph{to} Artix-7 FPGAs. During the development of the project, both of these were solved: Tristan Gingold released ghdlsynth-beta\cite{ghdlsynth-beta}, a bridge between GHDL\cite{ghdl} and yosys allowing VHDL to be synthesized just the same as Verilog, and Dave Shah added Xilinx support to nextpnr\cite{nextpnr-xilinx}. The latter was preceded by many months of volunteer work reverse-engineering the Xilinx bitstream format as part of \textit{Project X-Ray}\cite{prjxray}.
 
 With these two pieces in place, the project was switched over to a completely Free toolchain, removing any depencies on vendor tools:
 
@@ -77,7 +77,10 @@ With these two pieces in place, the project was switched over to a completely Fr
 
 The graphics submodule consists of a VGA timing generator, a text renderer with a font ROM, and a DVI encoder frontend:
 
+\begin{figure}[h]
 \includegraphics[width=\textwidth]{graphics.png}
+\caption{Block diagram of the video core}
+\end{figure}
 
 \subsubsection{VGA timing}
 
@@ -87,9 +90,10 @@ In analog screens, the electron beams (one for each primary color red, green and
 
 The same applies to vertical timings: after the beam reaches the end of the last line, a few off-screen Front Porch lines follow, then a pulse of the vsync (Vertical Sync) signal sends the beam to the top of the screen, where the first line of the next frame is drawn after several invisible Back Porch lines.
 
-\begin{center}
+\begin{figure}[h]
 \includegraphics[width=\textwidth]{vga_timing.png}
-\end{center}
+\caption{Diagram of VGA timing intervals}
+\end{figure}
 
 The VGA timing module generates these hsync and vsync signals, along with a blanking signal (active during any front porch, sync and back porch) and, while in the visible area (i.e. not blanking), the row and column of the current pixel relative to the visible area.
 
@@ -97,9 +101,10 @@ The VGA timing module generates these hsync and vsync signals, along with a blan
 
 The text renderer converts a logical representation of a character, such as its ASCII code (henceforth referred to as its \textit{codepoint}) to a visual representation (a \textit{glyph}). This conversion is achieved using a \textit{font}, a mapping of codepoints to glyphs.
 
-\begin{center}
+\begin{figure}[h]
 \includegraphics[width=0.7\textwidth]{text_renderer.png}
-\end{center}
+\caption{Block diagram of the text renderer}
+\end{figure}
 
 First, the current pixel coordinate (created by the VGA timing generator) is split up into two parts: the character index, which specifies the on-screen character the pixel belongs to, and the offset of the pixel in this character. The character index is passed to the text RAM, which contains the codepoint for each on-screen character. This codepoint, along with the pixel offset, is looked up in the font ROM to determine the color of the pixel.
 

vhdl_intro/vhdl_intro.tex

@@ -43,9 +43,10 @@ ghdl -r --std=08 counter_tb --wave=counter_tb.ghw
 gtkwave counter_tb.ghw counter_tb.gtkw
 \end{lstlisting}
 
-\begin{center}
+\begin{figure}
 \includegraphics[width=\textwidth]{counter_gtkwave.png}
-\end{center}
+\caption{Screenshot of the resulting waveform in GTKWave}
+\end{figure}
 
 \section{Synthesizing a design}