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Our diploma thesis
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Add information about DRAM interface
2020-03-29 18:05:05 +02:00
antrag Adeed tex files for dipl 2019-09-07 18:15:15 +02:00
pics Fix compilation, add gitignore 2020-03-23 13:20:25 +01:00
planung/DP Fix compilation, add gitignore 2020-03-23 13:20:25 +01:00
sections Add information about DRAM interface 2020-03-29 18:05:05 +02:00
.gitignore Merge batman content 2020-03-23 14:02:38 +01:00
Diplomschrift.bib Add information about DRAM interface 2020-03-29 18:05:05 +02:00
Diplomschrift.tex Merge batman content 2020-03-23 14:02:38 +01:00
generate_entity_headers.py Add Makefile and VHDL headers generation 2020-02-28 11:21:08 +01:00
LICENSE.md INITIAL COMMIT 2019-07-01 23:38:26 +02:00
Makefile Merge batman content 2020-03-23 14:02:38 +01:00
preamble.tex Improve FPGA comparison tables 2020-03-29 18:04:34 +02:00
README.md INITIAL COMMIT 2019-07-01 23:38:26 +02:00

README.md

About

This repository contains documents related to the YARM thesis at the HTBLuVA Innsbruck Anichstrasse.

LICENSE

This thesis is licensed for use under the Creative Commons BY 4.0 License as published by the Creative Commons Corporation. Please see the LICENSE.md file or the creative commons website at https://creativecommons.org/licenses/by/4.0/legalcode for a full copy of the license.