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Turn VHDL introduction into appendix

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Xiretza 2020-03-30 15:18:16 +02:00
parent 3dc6bbf390
commit 103a8e3d19
Signed by: xiretza
GPG key ID: E51A6C6A1EB378ED
3 changed files with 11 additions and 7 deletions
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7
Diplomschrift.tex
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@ -127,7 +127,6 @@ geschlechtsunabh"angig verstanden werden soll.
\clearpage
%\MR\input{sections/Kapitel/MR/EntwicklungAufgaben.tex}
\subfile{sections/vhdl_intro/vhdl_intro.tex}
\subfile{sections/soc/soc.tex}
\subfile{sections/core/core.tex}
@ -200,10 +199,14 @@ geschlechtsunabh"angig verstanden werden soll.
%\subsection{Projektterminplanung}
%\MR\input{sections/Anhang/Projektterminplanung/projektterminplanungMR.tex}
\clearpage
%\subsection{Arbeitsnachweis Diplomarbeit}
%\MR\input{sections/Anhang/Arbeitsnachweis/arbeitsnachweisMR.tex}
\begin{appendices}
\subfile{sections/vhdl_intro/vhdl_intro.tex}
\end{appendices}
\clearpage
\label{LastPage}
%\addtocontents{toc}{\protect\end{multicols}}
\end{document}

1
preamble.tex
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@ -340,3 +340,4 @@ minimum height=1cm, align=center, text width=3cm, draw=black, fill=blue!30]
\newcommand{\icode}[1]{\codeBox{\texttt{#1}}}
\usepackage{booktabs}
\usepackage[toc,page]{appendix}

10
sections/vhdl_intro/vhdl_intro.tex
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@ -1,11 +1,11 @@
\documentclass[../../Diplomschrift.tex]{subfiles}
\begin{document}
\part{A short introduction to VHDL}
\section{A short introduction to VHDL}
Designing a processor is a big task, and it's easiest to start very small. With software projects, this is usually in the form of a ``Hello World'' program - we will be designing a hardware equivalent of this.
\section{Prerequisites}
\subsection{Prerequisites}
Other than a text editor, the following Free Software packages have to be installed:
@ -21,7 +21,7 @@ Other than a text editor, the following Free Software packages have to be instal
\end{description}
\end{savenotes}
\section{Creating a design}
\subsection{Creating a design}
A simple starting design is an up/down counter. The following VHDL code describes the device:
@ -41,7 +41,7 @@ In order to test this design, a test bench has to be created:
title=\texttt{counter_tb.vhd},
]{vhdl/counter_tb.vhd}
\section{Simulating a design}
\subsection{Simulating a design}
\begin{lstlisting}[
style=terminal,
@ -62,7 +62,7 @@ gtkwave counter_tb.ghw counter_tb.gtkw
\caption{Screenshot of the counter test bench waveform in GTKWave}
\end{figure}
\section{Synthesizing a design}
\subsection{Synthesizing a design}
An additional Xilinx Design Constraints (XDC) file is required to assign the signals to pins on the FPGA: