Add initial outline of DS
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10 changed files with 435 additions and 0 deletions
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.gitignore
vendored
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.gitignore
vendored
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*.log
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*.aux
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*.synctex.gz
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*.pdf
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*.out
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*.o
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*.ghw
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*.gtkw
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work-*.cf
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15
Diplomschrift.tex
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Diplomschrift.tex
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\documentclass[a4paper,10pt]{article}
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\input{preamble.tex}
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\usepackage{subfiles}
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\begin{document}
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\tableofcontents
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\let\tableofcontents\relax
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\newpage
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\subfile{vhdl_intro/vhdl_intro.tex}
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\end{document}
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62
preamble.tex
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preamble.tex
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\usepackage[utf8]{inputenc}
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\usepackage{graphicx}
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\usepackage{url}
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\usepackage{listings}
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\lstdefinelanguage{customvhdl}[]{VHDL}{
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morekeywords=[2]{std_logic, std_logic_vector, natural, integer, bit, string},
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}
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numbers=left,
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title=\lstname,
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}
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\lstdefinestyle{vhdlstyle}{
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style=default,
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language=customvhdl,
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keywordstyle=[2]\bfseries\color{blue!80!white},
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backgroundcolor=\color{lightgray!20},
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frame=lrtb,
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}
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\lstset{
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style=vhdlstyle,
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}
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\usepackage{titling}
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\yyyymmdddate
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\renewcommand{\dateseparator}{-}
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\usepackage{pst-uml}
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\setlength{\hoffset}{30mm-1in}
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\setlength{\oddsidemargin}{0pt}
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\setlength{\textwidth}{\paperwidth-60mm}
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\addtolength{\textheight}{5em}
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\setlength{\headwidth}{\textwidth}
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\setlength{\topmargin}{0pt}
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\addtolength{\voffset}{-1em}
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\setlength{\parindent}{0px}
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\setlength{\parskip}{1em}
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\usepackage{footnote}
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% loaded last
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\usepackage{hyperref}
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62
vhdl_intro/d_flip_flop.pdf_tex
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vhdl_intro/d_flip_flop.pdf_tex
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vhdl_intro/d_flip_flop.svg
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After Width: | Height: | Size: 6.5 KiB |
BIN
vhdl_intro/flipflop_gtkwave.png
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BIN
vhdl_intro/flipflop_gtkwave.png
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Binary file not shown.
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After Width: | Height: | Size: 32 KiB |
25
vhdl_intro/vhdl/flipflop.vhd
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vhdl_intro/vhdl/flipflop.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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entity flipflop is
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port (
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d : in std_logic;
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e : in std_logic;
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q : out std_logic;
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q_n : out std_logic
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);
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end entity;
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architecture rtl of flipflop is
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signal state : std_logic;
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begin
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store: process(e)
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begin
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if rising_edge(e) then
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state <= d;
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end if;
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end process;
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q <= state;
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q_n <= not state;
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end architecture;
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BIN
vhdl_intro/vhdl/flipflop_tb
Executable file
BIN
vhdl_intro/vhdl/flipflop_tb
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Binary file not shown.
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vhdl_intro/vhdl/flipflop_tb.vhd
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vhdl_intro/vhdl/flipflop_tb.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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entity flipflop_tb is
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end entity;
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architecture test of flipflop_tb is
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signal s_d, s_e, s_q : std_logic;
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begin
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uut: entity work.flipflop
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port map (
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d => s_d,
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e => s_e,
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q => s_q
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);
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simulate: process
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begin
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s_d <= '0';
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s_e <= '0';
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wait for 100 ns;
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s_e <= '1';
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wait for 10 ns;
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s_e <= '0';
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assert s_q = '0';
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wait for 50 ns;
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s_d <= '1';
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wait for 50 ns;
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assert s_q = '0';
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s_e <= '1';
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wait for 10 ns;
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s_e <= '0';
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assert s_q = '1';
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wait for 100 ns;
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wait;
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end process;
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end architecture;
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52
vhdl_intro/vhdl_intro.tex
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52
vhdl_intro/vhdl_intro.tex
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\documentclass[../Diplomschrift.tex]{subfiles}
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\begin{document}
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\part{A short introduction to VHDL}
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Designing a processor is a big task, and it's easiest to start very small. With software projects, this is usually in the form of a ``Hello World'' program - we will be designing a hardware equivalent of this.
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\section{Prerequisites}
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Other than a text editor, the following Free Software packages have to be installed:
|
||||
|
||||
\begin{savenotes}
|
||||
\begin{description}
|
||||
\item[\texttt{ghdl}\footnote{\url{https://github.com/ghdl/ghdl}}] to compile and simulate the design
|
||||
\item[\texttt{gtkwave}\footnote{\url{http://gtkwave.sourceforge.net/}}] to view the generated waveform files
|
||||
\item[GNU \texttt{make}] to coordinate simulating designs, compiling firmware and generating images
|
||||
\item[python] for helper scripts
|
||||
\end{description}
|
||||
\end{savenotes}
|
||||
|
||||
\section{Creating a design}
|
||||
|
||||
A simple starting design is a D flip flop:
|
||||
|
||||
\def\svgwidth{2cm}
|
||||
\input{d_flip_flop.pdf_tex}
|
||||
|
||||
The following VHDL code describes the device:
|
||||
|
||||
\lstinputlisting[title=\texttt{flipflop.vhd}]{vhdl/flipflop.vhd}
|
||||
|
||||
In order to test this design, a test bench has to be created:
|
||||
|
||||
\lstinputlisting[title=\texttt{flipflop\_tb.vhd}]{vhdl/flipflop_tb.vhd}
|
||||
|
||||
\section{Simulating a design}
|
||||
|
||||
\begin{lstlisting}[style=default,language=sh]
|
||||
# analyze the design files
|
||||
ghdl -a *.vhd
|
||||
# elaborate the test bench entity
|
||||
ghdl -e flipflop_tb
|
||||
# run the test bench, saving the signal trace to a GHW file
|
||||
ghdl -r flipflop_tb --wave=flipflop_tb.ghw
|
||||
# open the trace with gtkwave
|
||||
gtkwave flipflop_tb.ghw
|
||||
\end{lstlisting}
|
||||
|
||||
\begin{center}
|
||||
\includegraphics[width=\textwidth]{flipflop_gtkwave.png}
|
||||
\end{center}
|
||||
\end{document}
|
||||
Loading…
Reference in a new issue