Update Hello World example, demonstrate synthesis
This commit is contained in:
parent
c4a71b39dd
commit
279e78331b
14 changed files with 206 additions and 315 deletions
1
.gitignore
vendored
1
.gitignore
vendored
|
|
@ -17,7 +17,6 @@
|
|||
|
||||
*.o
|
||||
*.ghw
|
||||
*.gtkw
|
||||
work-*.cf
|
||||
|
||||
svg-inkscape/
|
||||
|
|
|
|||
BIN
vhdl_intro/counter_gtkwave.png
Normal file
BIN
vhdl_intro/counter_gtkwave.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 40 KiB |
|
|
@ -1,62 +0,0 @@
|
|||
%% Creator: Inkscape inkscape 0.92.4, www.inkscape.org
|
||||
%% PDF/EPS/PS + LaTeX output extension by Johan Engelen, 2010
|
||||
%% Accompanies image file 'd_flip_flop.pdf' (pdf, eps, ps)
|
||||
%%
|
||||
%% To include the image in your LaTeX document, write
|
||||
%% \input{<filename>.pdf_tex}
|
||||
%% instead of
|
||||
%% \includegraphics{<filename>.pdf}
|
||||
%% To scale the image, write
|
||||
%% \def\svgwidth{<desired width>}
|
||||
%% \input{<filename>.pdf_tex}
|
||||
%% instead of
|
||||
%% \includegraphics[width=<desired width>]{<filename>.pdf}
|
||||
%%
|
||||
%% Images with a different path to the parent latex file can
|
||||
%% be accessed with the `import' package (which may need to be
|
||||
%% installed) using
|
||||
%% \usepackage{import}
|
||||
%% in the preamble, and then including the image with
|
||||
%% \import{<path to file>}{<filename>.pdf_tex}
|
||||
%% Alternatively, one can specify
|
||||
%% \graphicspath{{<path to file>/}}
|
||||
%%
|
||||
%% For more information, please see info/svg-inkscape on CTAN:
|
||||
%% http://tug.ctan.org/tex-archive/info/svg-inkscape
|
||||
%%
|
||||
\begingroup%
|
||||
\makeatletter%
|
||||
\providecommand\color[2][]{%
|
||||
\errmessage{(Inkscape) Color is used for the text in Inkscape, but the package 'color.sty' is not loaded}%
|
||||
\renewcommand\color[2][]{}%
|
||||
}%
|
||||
\providecommand\transparent[1]{%
|
||||
\errmessage{(Inkscape) Transparency is used (non-zero) for the text in Inkscape, but the package 'transparent.sty' is not loaded}%
|
||||
\renewcommand\transparent[1]{}%
|
||||
}%
|
||||
\providecommand\rotatebox[2]{#2}%
|
||||
\newcommand*\fsize{\dimexpr\f@size pt\relax}%
|
||||
\newcommand*\lineheight[1]{\fontsize{\fsize}{#1\fsize}\selectfont}%
|
||||
\ifx\svgwidth\undefined%
|
||||
\setlength{\unitlength}{67.5bp}%
|
||||
\ifx\svgscale\undefined%
|
||||
\relax%
|
||||
\else%
|
||||
\setlength{\unitlength}{\unitlength * \real{\svgscale}}%
|
||||
\fi%
|
||||
\else%
|
||||
\setlength{\unitlength}{\svgwidth}%
|
||||
\fi%
|
||||
\global\let\svgwidth\undefined%
|
||||
\global\let\svgscale\undefined%
|
||||
\makeatother%
|
||||
\begin{picture}(1,0.88888888)%
|
||||
\lineheight{1}%
|
||||
\setlength\tabcolsep{0pt}%
|
||||
\put(0,0){\includegraphics[width=\unitlength,page=1]{d_flip_flop.pdf}}%
|
||||
\put(0.24113854,0.61362848){\color[rgb]{0,0,0}\makebox(0,0)[lt]{\lineheight{0}\smash{\begin{tabular}[t]{l}D\end{tabular}}}}%
|
||||
\put(0.76564026,0.61111112){\color[rgb]{0,0,0}\makebox(0,0)[rt]{\lineheight{0}\smash{\begin{tabular}[t]{r}Q\end{tabular}}}}%
|
||||
\put(0.76472863,0.16666667){\color[rgb]{0,0,0}\makebox(0,0)[rt]{\lineheight{0}\smash{\begin{tabular}[t]{r}Q\end{tabular}}}}%
|
||||
\put(0.24113854,0.16666667){\color[rgb]{0,0,0}\makebox(0,0)[lt]{\lineheight{0}\smash{\begin{tabular}[t]{l}E\end{tabular}}}}%
|
||||
\end{picture}%
|
||||
\endgroup%
|
||||
|
|
@ -1,165 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!-- Created with Inkscape (http://www.inkscape.org/) -->
|
||||
<svg
|
||||
xmlns:dc="http://purl.org/dc/elements/1.1/"
|
||||
xmlns:cc="http://creativecommons.org/ns#"
|
||||
xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
|
||||
xmlns:svg="http://www.w3.org/2000/svg"
|
||||
xmlns="http://www.w3.org/2000/svg"
|
||||
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
|
||||
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
|
||||
width="100"
|
||||
height="100"
|
||||
id="svg2"
|
||||
sodipodi:version="0.32"
|
||||
inkscape:version="0.46"
|
||||
version="1.0"
|
||||
sodipodi:docbase="C:\Program Files\Inkscape"
|
||||
sodipodi:docname="Transparent Latch Symbol.svg"
|
||||
inkscape:output_extension="org.inkscape.output.svg.inkscape">
|
||||
<defs
|
||||
id="defs4">
|
||||
<inkscape:perspective
|
||||
sodipodi:type="inkscape:persp3d"
|
||||
inkscape:vp_x="0 : 50 : 1"
|
||||
inkscape:vp_y="0 : 1000 : 0"
|
||||
inkscape:vp_z="100 : 50 : 1"
|
||||
inkscape:persp3d-origin="50 : 33.333333 : 1"
|
||||
id="perspective3848" />
|
||||
</defs>
|
||||
<sodipodi:namedview
|
||||
id="base"
|
||||
pagecolor="#ffffff"
|
||||
bordercolor="#666666"
|
||||
borderopacity="1.0"
|
||||
inkscape:pageopacity="0.0"
|
||||
inkscape:pageshadow="2"
|
||||
inkscape:zoom="2"
|
||||
inkscape:cx="69.170212"
|
||||
inkscape:cy="11.088566"
|
||||
inkscape:document-units="px"
|
||||
inkscape:current-layer="layer1"
|
||||
showgrid="true"
|
||||
inkscape:grid-bbox="true"
|
||||
inkscape:grid-points="true"
|
||||
showguides="true"
|
||||
inkscape:guide-bbox="true"
|
||||
gridtolerance="5px"
|
||||
inkscape:window-width="1024"
|
||||
inkscape:window-height="712"
|
||||
inkscape:window-x="94"
|
||||
inkscape:window-y="107"
|
||||
inkscape:snap-bbox="true"
|
||||
objecttolerance="11">
|
||||
<inkscape:grid
|
||||
id="GridFromPre046Settings"
|
||||
type="xygrid"
|
||||
originx="0px"
|
||||
originy="0px"
|
||||
spacingx="5px"
|
||||
spacingy="5px"
|
||||
color="#0000ff"
|
||||
empcolor="#0000ff"
|
||||
opacity="0.2"
|
||||
empopacity="0.4"
|
||||
empspacing="5"
|
||||
visible="true"
|
||||
enabled="true" />
|
||||
</sodipodi:namedview>
|
||||
<metadata
|
||||
id="metadata7">
|
||||
<rdf:RDF>
|
||||
<cc:Work
|
||||
rdf:about="">
|
||||
<dc:format>image/svg+xml</dc:format>
|
||||
<dc:type
|
||||
rdf:resource="http://purl.org/dc/dcmitype/StillImage" />
|
||||
</cc:Work>
|
||||
</rdf:RDF>
|
||||
</metadata>
|
||||
<g
|
||||
inkscape:label="Layer 1"
|
||||
inkscape:groupmode="layer"
|
||||
id="layer1">
|
||||
<g
|
||||
id="g4867"
|
||||
style="fill:none">
|
||||
<rect
|
||||
y="11.500001"
|
||||
x="21.499998"
|
||||
height="77"
|
||||
width="56.999996"
|
||||
id="rect1311"
|
||||
style="opacity:1;fill:none;fill-opacity:0.03703703;stroke:#000000;stroke-width:2.99999952;stroke-linecap:square;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" />
|
||||
<path
|
||||
id="path3085"
|
||||
d="M 21,30 L 5,30"
|
||||
style="fill:none;fill-opacity:0.75;fill-rule:evenodd;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1"
|
||||
sodipodi:nodetypes="cc" />
|
||||
<path
|
||||
id="path3087"
|
||||
d="M 21,70 L 5,70"
|
||||
style="fill:none;fill-opacity:0.75;fill-rule:evenodd;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1"
|
||||
sodipodi:nodetypes="cc" />
|
||||
<path
|
||||
id="path3089"
|
||||
d="M 79,70 L 95,70"
|
||||
style="fill:none;fill-opacity:0.75;fill-rule:evenodd;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1"
|
||||
sodipodi:nodetypes="cc" />
|
||||
<path
|
||||
id="path3091"
|
||||
d="M 79,30 L 95,30"
|
||||
style="fill:none;fill-opacity:0.75;fill-rule:evenodd;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1"
|
||||
sodipodi:nodetypes="cc" />
|
||||
</g>
|
||||
<path
|
||||
sodipodi:nodetypes="cc"
|
||||
style="fill:none;fill-opacity:0.75;fill-rule:evenodd;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
|
||||
d="M 63.806565,62 L 73.306565,62"
|
||||
id="path3081" />
|
||||
<text
|
||||
xml:space="preserve"
|
||||
style="font-size:14px;font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;text-align:start;line-height:100%;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;font-family:DejaVu Sans;-inkscape-font-specification:DejaVu Sans"
|
||||
x="26.702469"
|
||||
y="34.773438"
|
||||
id="text3850"
|
||||
sodipodi:linespacing="100%"><tspan
|
||||
sodipodi:role="line"
|
||||
id="tspan3852"
|
||||
x="26.702469"
|
||||
y="34.773438">D</tspan></text>
|
||||
<text
|
||||
xml:space="preserve"
|
||||
style="font-size:14px;font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;text-align:end;line-height:100%;writing-mode:lr-tb;text-anchor:end;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;font-family:DejaVu Sans;-inkscape-font-specification:DejaVu Sans"
|
||||
x="73.907623"
|
||||
y="35"
|
||||
id="text3858"
|
||||
sodipodi:linespacing="100%"><tspan
|
||||
sodipodi:role="line"
|
||||
id="tspan3860"
|
||||
x="73.907623"
|
||||
y="35">Q</tspan></text>
|
||||
<text
|
||||
xml:space="preserve"
|
||||
style="font-size:14px;font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;text-align:end;line-height:100%;writing-mode:lr-tb;text-anchor:end;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;font-family:DejaVu Sans;-inkscape-font-specification:DejaVu Sans"
|
||||
x="73.825577"
|
||||
y="75"
|
||||
id="text3863"
|
||||
sodipodi:linespacing="100%"><tspan
|
||||
sodipodi:role="line"
|
||||
id="tspan3865"
|
||||
x="73.825577"
|
||||
y="75">Q</tspan></text>
|
||||
<text
|
||||
sodipodi:linespacing="100%"
|
||||
id="text4661"
|
||||
y="75"
|
||||
x="26.702469"
|
||||
style="font-size:14px;font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;text-align:start;line-height:100%;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;font-family:DejaVu Sans;-inkscape-font-specification:DejaVu Sans"
|
||||
xml:space="preserve"><tspan
|
||||
y="75"
|
||||
x="26.702469"
|
||||
id="tspan4663"
|
||||
sodipodi:role="line">E</tspan></text>
|
||||
</g>
|
||||
</svg>
|
||||
|
Before Width: | Height: | Size: 6.5 KiB |
Binary file not shown.
|
Before Width: | Height: | Size: 32 KiB |
5
vhdl_intro/vhdl/.gitignore
vendored
Normal file
5
vhdl_intro/vhdl/.gitignore
vendored
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
*.json
|
||||
*.fasm
|
||||
*.frames
|
||||
*.bit
|
||||
counter_tb
|
||||
33
vhdl_intro/vhdl/counter.vhd
Normal file
33
vhdl_intro/vhdl/counter.vhd
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity counter is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
reset : in std_logic;
|
||||
enable : in std_logic;
|
||||
direction : in std_logic;
|
||||
|
||||
count_out : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end counter;
|
||||
|
||||
architecture behaviour of counter is
|
||||
signal count : unsigned(7 downto 0) := (others => '0');
|
||||
begin
|
||||
proc: process(clk)
|
||||
begin
|
||||
if reset then
|
||||
count <= (others => '0');
|
||||
elsif rising_edge(clk) and enable = '1' then
|
||||
if direction = '1' then
|
||||
count <= count + 1;
|
||||
else
|
||||
count <= count - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
count_out <= std_logic_vector(count);
|
||||
end behaviour;
|
||||
27
vhdl_intro/vhdl/counter.xdc
Normal file
27
vhdl_intro/vhdl/counter.xdc
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
set_property LOC D9 [get_ports clk]
|
||||
set_property LOC C9 [get_ports reset]
|
||||
set_property LOC A8 [get_ports enable]
|
||||
set_property LOC C11 [get_ports direction]
|
||||
|
||||
set_property LOC F6 [get_ports count_out[0]]
|
||||
set_property LOC J4 [get_ports count_out[1]]
|
||||
set_property LOC J2 [get_ports count_out[2]]
|
||||
set_property LOC H6 [get_ports count_out[3]]
|
||||
set_property LOC H5 [get_ports count_out[4]]
|
||||
set_property LOC J5 [get_ports count_out[5]]
|
||||
set_property LOC T9 [get_ports count_out[6]]
|
||||
set_property LOC T10 [get_ports count_out[7]]
|
||||
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports clk]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports reset]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports enable]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports direction]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports count_out[0]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports count_out[1]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports count_out[2]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports count_out[3]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports count_out[4]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports count_out[5]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports count_out[6]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports count_out[7]]
|
||||
|
||||
30
vhdl_intro/vhdl/counter_tb.gtkw
Normal file
30
vhdl_intro/vhdl/counter_tb.gtkw
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
[*]
|
||||
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
|
||||
[*] Fri Mar 6 16:40:57 2020
|
||||
[*]
|
||||
[dumpfile] "/home/xiretza/Nextcloud/School/Diplomarbeit/Diplomschrift/vhdl_intro/vhdl/counter_tb.ghw"
|
||||
[dumpfile_mtime] "Fri Mar 6 16:40:14 2020"
|
||||
[dumpfile_size] 814
|
||||
[savefile] "/home/xiretza/Nextcloud/School/Diplomarbeit/Diplomschrift/vhdl_intro/vhdl/counter_tb.gtkw"
|
||||
[timestart] 0
|
||||
[size] 910 543
|
||||
[pos] 357 86
|
||||
*-25.819012 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
[treeopen] top.
|
||||
[treeopen] top.counter_tb.
|
||||
[treeopen] top.counter_tb.uut.
|
||||
[sst_width] 221
|
||||
[signals_width] 169
|
||||
[sst_expanded] 1
|
||||
[sst_vpaned_height] 125
|
||||
@28
|
||||
top.counter_tb.uut.clk
|
||||
top.counter_tb.uut.reset
|
||||
top.counter_tb.uut.enable
|
||||
top.counter_tb.uut.direction
|
||||
@200
|
||||
-
|
||||
@24
|
||||
#{top.counter_tb.count_out[7:0]} top.counter_tb.count_out[7] top.counter_tb.count_out[6] top.counter_tb.count_out[5] top.counter_tb.count_out[4] top.counter_tb.count_out[3] top.counter_tb.count_out[2] top.counter_tb.count_out[1] top.counter_tb.count_out[0]
|
||||
[pattern_trace] 1
|
||||
[pattern_trace] 0
|
||||
71
vhdl_intro/vhdl/counter_tb.vhd
Normal file
71
vhdl_intro/vhdl/counter_tb.vhd
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity counter_tb is
|
||||
end counter_tb;
|
||||
|
||||
architecture test of counter_tb is
|
||||
signal clk, reset, enable, direction : std_logic;
|
||||
signal s_count_out : std_logic_vector(7 downto 0);
|
||||
|
||||
signal count_out : unsigned(7 downto 0);
|
||||
begin
|
||||
uut: entity work.counter
|
||||
port map (
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
enable => enable,
|
||||
direction => direction,
|
||||
|
||||
count_out => s_count_out
|
||||
);
|
||||
|
||||
count_out <= unsigned(s_count_out);
|
||||
|
||||
simulate: process
|
||||
begin
|
||||
clk <= '0';
|
||||
reset <= '1';
|
||||
enable <= '0';
|
||||
|
||||
wait for 30 ns;
|
||||
assert count_out = 0;
|
||||
|
||||
reset <= '0';
|
||||
|
||||
clk <= '0';
|
||||
wait for 10 ns;
|
||||
clk <= '1';
|
||||
wait for 10 ns;
|
||||
|
||||
assert count_out = 0;
|
||||
|
||||
enable <= '1';
|
||||
direction <= '0';
|
||||
|
||||
clk <= '0';
|
||||
wait for 10 ns;
|
||||
clk <= '1';
|
||||
wait for 10 ns;
|
||||
|
||||
assert count_out = 255;
|
||||
|
||||
direction <= '1';
|
||||
|
||||
clk <= '0';
|
||||
wait for 10 ns;
|
||||
clk <= '1';
|
||||
wait for 10 ns;
|
||||
|
||||
clk <= '0';
|
||||
wait for 10 ns;
|
||||
clk <= '1';
|
||||
wait for 10 ns;
|
||||
|
||||
assert count_out = 1;
|
||||
|
||||
wait for 30 ns;
|
||||
wait;
|
||||
end process;
|
||||
end test;
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
entity flipflop is
|
||||
port (
|
||||
d : in std_logic;
|
||||
e : in std_logic;
|
||||
q : out std_logic;
|
||||
q_n : out std_logic
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture rtl of flipflop is
|
||||
signal state : std_logic;
|
||||
begin
|
||||
store: process(e)
|
||||
begin
|
||||
if rising_edge(e) then
|
||||
state <= d;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
q <= state;
|
||||
q_n <= not state;
|
||||
end architecture;
|
||||
Binary file not shown.
|
|
@ -1,44 +0,0 @@
|
|||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
entity flipflop_tb is
|
||||
end entity;
|
||||
|
||||
architecture test of flipflop_tb is
|
||||
signal s_d, s_e, s_q : std_logic;
|
||||
begin
|
||||
uut: entity work.flipflop
|
||||
port map (
|
||||
d => s_d,
|
||||
e => s_e,
|
||||
q => s_q
|
||||
);
|
||||
|
||||
simulate: process
|
||||
begin
|
||||
s_d <= '0';
|
||||
s_e <= '0';
|
||||
|
||||
wait for 100 ns;
|
||||
|
||||
s_e <= '1';
|
||||
wait for 10 ns;
|
||||
s_e <= '0';
|
||||
|
||||
assert s_q = '0';
|
||||
|
||||
wait for 50 ns;
|
||||
s_d <= '1';
|
||||
wait for 50 ns;
|
||||
|
||||
assert s_q = '0';
|
||||
|
||||
s_e <= '1';
|
||||
wait for 10 ns;
|
||||
s_e <= '0';
|
||||
assert s_q = '1';
|
||||
|
||||
wait for 100 ns;
|
||||
wait;
|
||||
end process;
|
||||
end architecture;
|
||||
|
|
@ -11,42 +11,64 @@ Other than a text editor, the following Free Software packages have to be instal
|
|||
|
||||
\begin{savenotes}
|
||||
\begin{description}
|
||||
\item[\icode{ghdl}\footnote{\url{https://github.com/ghdl/ghdl}}] to compile and simulate the design
|
||||
\item[\icode{gtkwave}\footnote{\url{http://gtkwave.sourceforge.net/}}] to view the generated waveform files
|
||||
\item[GNU \icode{make}] to coordinate simulating designs, compiling firmware and generating images
|
||||
\item[\icode{python}] for helper scripts
|
||||
\item[\icode{ghdl}\footnote{\url{https://github.com/ghdl/ghdl}}] to analyze, compile, and simulate the design
|
||||
\item[\icode{gtkwave}\footnote{\url{http://gtkwave.sourceforge.net/}}] to view the simulation waveform files
|
||||
\item[\icode{yosys}\footnote{\url{http://www.clifford.at/yosys/}}] to synthesize the design
|
||||
\item[\icode{nextpnr-xilinx}\footnote{\url{https://github.com/daveshah1/nextpnr-xilinx}}] to place and route the design
|
||||
\item[\icode{Project X-Ray}\footnote{\url{https://github.com/SymbiFlow/prjxray}}] for FPGA layout data and bitstream tools
|
||||
\item[\icode{xc3sprog}\footnote{\url{https://sourceforge.net/projects/xc3sprog/}}] to load the bitstream onto the FPGA
|
||||
\end{description}
|
||||
\end{savenotes}
|
||||
|
||||
\section{Creating a design}
|
||||
|
||||
A simple starting design is a D flip flop:
|
||||
A simple starting design is an up/down counter. The following VHDL code describes the device:
|
||||
|
||||
\def\svgwidth{2cm}
|
||||
\input{d_flip_flop.pdf_tex}
|
||||
|
||||
The following VHDL code describes the device:
|
||||
|
||||
\lstinputlisting[title=\texttt{flipflop.vhd}]{vhdl/flipflop.vhd}
|
||||
\lstinputlisting[title=\texttt{counter.vhd}]{vhdl/counter.vhd}
|
||||
|
||||
In order to test this design, a test bench has to be created:
|
||||
|
||||
\lstinputlisting[title=\texttt{flipflop\_tb.vhd}]{vhdl/flipflop_tb.vhd}
|
||||
\lstinputlisting[title=\texttt{counter\_tb.vhd}]{vhdl/counter_tb.vhd}
|
||||
|
||||
\section{Simulating a design}
|
||||
|
||||
\begin{lstlisting}[style=default,language=sh]
|
||||
# analyze the design files
|
||||
ghdl -a *.vhd
|
||||
ghdl -a --std=08 *.vhd
|
||||
# elaborate the test bench entity
|
||||
ghdl -e flipflop_tb
|
||||
ghdl -e --std=08 counter_tb
|
||||
# run the test bench, saving the signal trace to a GHW file
|
||||
ghdl -r flipflop_tb --wave=flipflop_tb.ghw
|
||||
# open the trace with gtkwave
|
||||
gtkwave flipflop_tb.ghw
|
||||
ghdl -r --std=08 counter_tb --wave=counter_tb.ghw
|
||||
# open the trace with gtkwave (using the view configuration in counter_tb.gtkw)
|
||||
gtkwave counter_tb.ghw counter_tb.gtkw
|
||||
\end{lstlisting}
|
||||
|
||||
\begin{center}
|
||||
\includegraphics[width=\textwidth]{flipflop_gtkwave.png}
|
||||
\includegraphics[width=\textwidth]{counter_gtkwave.png}
|
||||
\end{center}
|
||||
|
||||
\section{Synthesizing a design}
|
||||
|
||||
An additional Xilinx Design Constraints (XDC) file is required to assign the signals to pins on the FPGA:
|
||||
|
||||
\lstinputlisting[style=default,title=\texttt{counter.xdc}]{vhdl/counter.xdc}
|
||||
|
||||
\begin{lstlisting}[style=default,language=sh]
|
||||
# synthesize with yosys
|
||||
yosys -m ghdl.so -p '
|
||||
ghdl --std=08 counter.vhd -e counter;
|
||||
synth_xilinx -flatten;
|
||||
write_json counter.json'
|
||||
# place and route the design with nextpnr
|
||||
nextpnr-xilinx --chipdb xc7a35tcsg324-1.bin --xdc counter.xdc --json counter.json --fasm counter.fasm
|
||||
# convert the FPGA assembly to frames
|
||||
fasm2frames.py --part xc7a35tcsg324-1 counter.fasm counter.frames
|
||||
# convert the frames to a bitstream
|
||||
xc7frames2bit --part-name xc7a35tcsg324-1 --frm-file counter.frames --output-file counter.bit
|
||||
# upload the bitstream to the FPGA
|
||||
xc3sprog -c nexys4 counter.bit
|
||||
\end{lstlisting}
|
||||
|
||||
The current value of the counter is displayed in binary on the eight LEDs on the board. When switch 0 (enable) is in the high position, the counter can be advanced using button 0, with the direction set by switch 1. Button 1 resets the counter to zero.
|
||||
|
||||
\end{document}
|
||||
|
|
|
|||
Loading…
Reference in a new issue