Our diploma thesis

Xiretza 279e78331b Update Hello World example, demonstrate synthesis		2020-03-20 10:16:40 +01:00
core	Misc updates, add core and SoC docs	2020-03-01 17:13:51 +01:00
pics	Initial import	2019-09-20 17:32:06 +02:00
soc	Misc updates, add core and SoC docs	2020-03-01 17:13:51 +01:00
vhdl_intro	Update Hello World example, demonstrate synthesis	2020-03-20 10:16:40 +01:00
.gitignore	Update Hello World example, demonstrate synthesis	2020-03-20 10:16:40 +01:00
Diplomschrift.bib	Misc updates, add core and SoC docs	2020-03-01 17:13:51 +01:00
Diplomschrift.tex	Misc updates, add core and SoC docs	2020-03-01 17:13:51 +01:00
Diplomschrift_original.tex	Move sample DS	2019-12-10 14:23:44 +01:00
generate_entity_headers.py	Add Makefile and VHDL headers generation	2020-02-28 11:21:08 +01:00
Makefile	Add Makefile and VHDL headers generation	2020-02-28 11:21:08 +01:00
preamble.tex	Misc updates, add core and SoC docs	2020-03-01 17:13:51 +01:00