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103a8e3d19
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Turn VHDL introduction into appendix
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2020-03-30 15:18:16 +02:00 |
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3dc6bbf390
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Misc fixes and improvements
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2020-03-29 22:01:05 +02:00 |
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ffb1fe4060
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Add citations for GitLab CI and RISC-V spec
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2020-03-29 21:58:14 +02:00 |
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254a064680
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Check all citation links and add urldate=
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2020-03-29 21:57:24 +02:00 |
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3b65229eae
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Add information about formal verification
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2020-03-29 19:03:49 +02:00 |
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e891568008
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Small fixes
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2020-03-29 18:05:21 +02:00 |
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40bc2327fd
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Add information about DRAM interface
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2020-03-29 18:05:05 +02:00 |
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89f0a1565e
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Improve FPGA comparison tables
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2020-03-29 18:04:34 +02:00 |
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239106c2fd
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Add nbsp before citations
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2020-03-29 18:03:16 +02:00 |
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dc77d4bf61
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Add labels and captions to listings
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2020-03-27 14:20:22 +01:00 |
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ad723217ad
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Add information about external bus
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2020-03-27 12:50:24 +01:00 |
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244380ee5f
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Fix citations, change citation style
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2020-03-27 12:49:50 +01:00 |
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e65030ef47
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Add information about riscv compliance tests
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2020-03-27 12:49:38 +01:00 |
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ed378c0917
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Merge batman content
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2020-03-23 14:02:38 +01:00 |
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1cb525748f
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Fix compilation, add gitignore
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2020-03-23 13:20:25 +01:00 |
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bf239165f8
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Cite more sources, use figures for graphics
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2020-03-21 14:35:11 +01:00 |
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52f3c6b0a7
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Add information about ws2812 driver
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2020-03-21 14:27:34 +01:00 |
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e685cdea10
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Fix Eater CPU publication year in bibliography
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2020-03-20 10:19:31 +01:00 |
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279e78331b
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Update Hello World example, demonstrate synthesis
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2020-03-20 10:16:40 +01:00 |
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c4a71b39dd
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Misc updates, add core and SoC docs
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2020-03-01 17:13:51 +01:00 |
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9d04e5ca2b
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Update gitignore
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2020-02-28 18:35:54 +01:00 |
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ae4c533320
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Add bibliography
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2020-02-28 18:35:10 +01:00 |
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38e12fa78b
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Add Makefile and VHDL headers generation
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2020-02-28 11:21:08 +01:00 |
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387e9d61c6
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Add initial outline of DS
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2019-12-10 15:32:02 +01:00 |
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3b360e3237
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Move sample DS
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2019-12-10 14:23:44 +01:00 |
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b9fa071e76
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Initial import
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2019-09-20 17:32:06 +02:00 |
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35b62c8251
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Adeed tex files for dipl
Signed-off-by: Tyrolyean <tyrolyean@tyrolyean.net>
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2019-09-07 18:15:15 +02:00 |
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bb9d39a95d
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Added correction and corrected version
as given by the allmighty XH. All behail him!
Signed-off-by: Tyrolyean <tyrolyean@tyrolyean.net>
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2019-07-01 23:41:19 +02:00 |
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6e711be18f
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Added initial antrag
Signed-off-by: Tyrolyean <tyrolyean@tyrolyean.net>
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2019-07-01 23:40:11 +02:00 |
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b7fae59d8e
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INITIAL COMMIT
Signed-off-by: Tyrolyean <tyrolyean@tyrolyean.net>
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2019-07-01 23:38:26 +02:00 |
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