Commit graph

20 commits

Author SHA1 Message Date
Xiretza 99e52e611e fix: add license 2022-06-21 07:21:16 +02:00
Xiretza 87ef826ad2 fix: work around ghdl#2102
https://github.com/ghdl/ghdl/issues/2102
2022-06-20 13:15:22 +02:00
Xiretza e25e8a958d fix: work around ghdl#2078
https://github.com/ghdl/ghdl/issues/2078
2022-06-20 13:15:22 +02:00
Xiretza 498089d468 fix: work around ghdl#2077
https://github.com/ghdl/ghdl/issues/2077
2022-06-20 13:15:06 +02:00
Xiretza a9a1797236 feat: double buffering 2022-06-20 13:11:31 +02:00
Xiretza e8476445b2 fix: use parallel ws2812 driver 2022-06-18 17:24:47 +02:00
Xiretza 645a838a73 vhdl: use UDP packet length 2022-06-07 07:34:09 +02:00
Xiretza 70a7b0520a vhdl: only run encoders once all pixels are received 2022-06-07 07:34:09 +02:00
Xiretza 0f497e76e8 vhdl: implement bounds checking for strand number 2022-06-07 07:34:09 +02:00
Xiretza 4bced13726 vhdl: implement magic number on receive 2022-06-06 17:11:39 +02:00
Xiretza 904f34f4d4 vhdl: implement frame number checking 2022-06-06 16:45:16 +02:00
Xiretza 4d07ec3fa1 vhdl: reorganize receive FSM to avoid ghdl issues
https://github.com/ghdl/ghdl/issues/2077
https://github.com/ghdl/ghdl/issues/2078
2022-06-06 15:24:49 +02:00
Xiretza 40caa85d92 vhdl: implement multiple strands 2022-06-06 12:58:41 +02:00
Xiretza 24e3b11588 Use little endian byte order in network streams 2022-06-06 10:29:45 +02:00
Xiretza ccd911dc1e vhdl: implement feedback packets 2022-06-05 22:56:29 +02:00
Xiretza d0e65a3126 vhdl: remove unused signals 2022-06-05 22:27:16 +02:00
Xiretza 9121ccfdbe vhdl: implement setting LEDs via UDP 2022-06-05 21:36:10 +02:00
Xiretza d5b0ee2cfa vhdl: rename NUM_DRIVERS to NUM_STRANDS 2022-06-05 21:36:10 +02:00
Xiretza 57e6daedcc vhdl: move ws2812 driver to splink module 2022-06-05 21:36:10 +02:00
Xiretza d6687786a7 Add basic tools and VHDL skeleton 2022-06-03 19:11:07 +02:00