50 lines
861 B
VHDL
50 lines
861 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity splink is
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generic (
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NUM_STRANDS : positive;
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MAX_STRAND_LEN : positive := 256
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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drivers : out std_logic_vector(NUM_STRANDS-1 downto 0)
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);
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end entity;
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architecture a of splink is
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signal driver_out : std_logic;
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begin
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ws2812_inst: entity work.ws2812
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generic map (
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NUM_LEDS => 20,
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COLOR_ORDER => "GRB",
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T_CLK => 12.5 ns,
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T0H => 0.35 us,
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T0L => 0.8 us,
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T1H => 0.7 us,
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T1L => 0.6 us,
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T_RES => 80 us
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)
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port map (
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n_reset => not reset,
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clk => clk,
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led_addr => open,
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led_red => x"ff",
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led_green => x"00",
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led_blue => x"ff",
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dout => driver_out
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);
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-- https://github.com/YosysHQ/yosys/issues/3360
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drivers <= (19 => driver_out, others => '0');
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end architecture;
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