37 lines
695 B
VHDL
37 lines
695 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity splink is
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generic (
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NUM_DRIVERS : positive := 16;
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ROWS : positive := 100;
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COLS : positive := 100
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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drivers : out std_logic_vector(NUM_DRIVERS-1 downto 0)
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);
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end entity;
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architecture a of splink is
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signal count2: unsigned(3 downto 0);
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signal count: natural range 0 to 10000000;
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begin
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process(clk)
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begin
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if rising_edge(clk) then
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if count = 10000000 then
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count <= 0;
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count2 <= count2 + 1;
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else
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count <= count + 1;
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end if;
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end if;
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end process;
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drivers <= (15 downto 4 => '0') & std_logic_vector(count2);
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end architecture;
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