88 lines
2 KiB
VHDL
88 lines
2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity splink is
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generic (
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NUM_STRANDS : positive;
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MAX_STRAND_LEN : positive := 256
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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udp_src_ip_address : in std_logic_vector(31 downto 0);
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udp_src_port : in std_logic_vector(15 downto 0);
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udp_length : in std_logic_vector(15 downto 0);
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udp_valid : in std_logic;
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udp_last : in std_logic;
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udp_last_be : in std_logic_vector(3 downto 0);
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udp_ready : out std_logic;
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udp_data : in std_logic_vector(31 downto 0);
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drivers : out std_logic_vector(NUM_STRANDS-1 downto 0)
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);
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end entity;
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architecture a of splink is
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signal driver_out : std_logic;
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constant BITS_PER_LED: natural := 24;
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subtype color_t is std_logic_vector(BITS_PER_LED-1 downto 0);
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type strand_store_t is array(0 to MAX_STRAND_LEN) of color_t;
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signal strand_store: strand_store_t;
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signal led_addr : std_logic_vector(7 downto 0);
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signal current_color : color_t;
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begin
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ws2812_inst: entity work.ws2812
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generic map (
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NUM_LEDS => MAX_STRAND_LEN,
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COLOR_ORDER => "GRB",
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T_CLK => 12.5 ns,
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T0H => 0.35 us,
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T0L => 0.8 us,
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T1H => 0.7 us,
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T1L => 0.6 us,
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T_RES => 80 us
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)
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port map (
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n_reset => not reset,
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clk => clk,
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led_addr => led_addr,
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led_red => current_color(7 downto 0),
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led_green => current_color(15 downto 8),
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led_blue => current_color(23 downto 16),
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dout => driver_out
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);
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-- https://github.com/YosysHQ/yosys/issues/3360
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drivers <= (19 => driver_out, others => '0');
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writer: process(clk)
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variable store_counter: natural range 0 to MAX_STRAND_LEN-1;
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begin
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if rising_edge(clk) then
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current_color <= strand_store(to_integer(unsigned(led_addr)));
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if udp_valid then
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strand_store(store_counter) <= udp_data(23 downto 0);
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if udp_last then
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store_counter := 0;
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elsif store_counter /= MAX_STRAND_LEN-1 then
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store_counter := store_counter + 1;
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end if;
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end if;
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end if;
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end process;
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udp_ready <= '1';
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end architecture;
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