128 lines
3 KiB
VHDL
128 lines
3 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity splink is
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generic (
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NUM_STRANDS : positive;
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MAX_STRAND_LEN : positive := 256
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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udp_valid : in std_logic;
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udp_last : in std_logic;
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udp_data : in std_logic_vector(31 downto 0);
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frame_done : out std_logic;
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drivers : out std_logic_vector(NUM_STRANDS-1 downto 0)
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);
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end entity;
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architecture a of splink is
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constant BITS_PER_LED: natural := 24;
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subtype color_t is std_logic_vector(BITS_PER_LED-1 downto 0);
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type led_data_t is record
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addr : std_logic_vector(7 downto 0);
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current_color : color_t;
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was_written : std_logic;
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end record;
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type led_data_arr_t is array(0 to NUM_STRANDS-1) of led_data_t;
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signal led_data_arr : led_data_arr_t;
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begin
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driver_gen: for i in 0 to NUM_STRANDS-1 generate
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ws2812_inst: entity work.ws2812
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generic map (
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NUM_LEDS => MAX_STRAND_LEN,
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COLOR_ORDER => "GRB",
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T_CLK => 12.5 ns,
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T0H => 0.35 us,
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T0L => 0.8 us,
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T1H => 0.7 us,
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T1L => 0.6 us,
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T_RES => 80 us
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)
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port map (
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n_reset => not reset,
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clk => clk,
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led_addr => led_data_arr(i).addr,
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led_red => led_data_arr(i).current_color(23 downto 16),
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led_green => led_data_arr(i).current_color(15 downto 8),
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led_blue => led_data_arr(i).current_color(7 downto 0),
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dout => drivers(i)
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);
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end generate;
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writer: process(clk)
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type strand_store_t is array(0 to MAX_STRAND_LEN-1) of color_t;
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type strand_stores_t is array(0 to NUM_STRANDS-1) of strand_store_t;
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variable strand_stores: strand_stores_t;
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variable active_strand: natural range 0 to NUM_STRANDS-1;
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variable packet_len: natural range 1 to MAX_STRAND_LEN;
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variable frame_number: unsigned(31 downto 0);
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variable store_counter: natural range 0 to MAX_STRAND_LEN-1;
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type receive_state_t is (FRAME_NUM, STRAND_NUM, DATA, DROP);
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variable receive_state : receive_state_t;
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begin
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if rising_edge(clk) then
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frame_done <= '0';
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for i in 0 to NUM_STRANDS-1 loop
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led_data_arr(i).current_color <= strand_stores(i)(to_integer(unsigned(led_data_arr(i).addr)));
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end loop;
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if udp_valid then
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case receive_state is
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when STRAND_NUM =>
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-- TODO udp_length, range check with MAX_STRAND_LEN
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packet_len := MAX_STRAND_LEN;
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-- FIXME bounds check
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active_strand := to_integer(unsigned(udp_data));
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receive_state := FRAME_NUM;
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when FRAME_NUM =>
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frame_number := unsigned(udp_data);
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store_counter := 0;
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receive_state := DATA;
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when DATA =>
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strand_stores(active_strand)(store_counter) := udp_data(23 downto 0);
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if store_counter = packet_len then
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if udp_last then
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--led_data_arr(active_strand).was_written <= '1';
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else
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-- packet too long
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receive_state := DROP;
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end if;
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else
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store_counter := store_counter + 1;
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end if;
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when DROP =>
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-- wait until udp_last
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end case;
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if udp_last then
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receive_state := STRAND_NUM;
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end if;
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end if;
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end if;
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end process;
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end architecture;
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