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21 Commits 5 Branches 0 Tags 123 MiB
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21 Commits

Author SHA1 Message Date
Xiretza 8492d24c27
Release batman-2020-03-27 2020-03-27 12:52:42 +01:00
Xiretza ad723217ad
Add information about external bus 2020-03-27 12:50:24 +01:00
Xiretza 244380ee5f
Fix citations, change citation style 2020-03-27 12:49:50 +01:00
Xiretza e65030ef47
Add information about riscv compliance tests 2020-03-27 12:49:38 +01:00
Xiretza ed378c0917
Merge batman content 2020-03-23 14:02:38 +01:00
Xiretza 1cb525748f
Fix compilation, add gitignore 2020-03-23 13:20:25 +01:00
Xiretza bf239165f8
Cite more sources, use figures for graphics 2020-03-21 14:35:11 +01:00
Xiretza 52f3c6b0a7
Add information about ws2812 driver 2020-03-21 14:27:34 +01:00
Xiretza e685cdea10
Fix Eater CPU publication year in bibliography 2020-03-20 10:19:31 +01:00
Xiretza 279e78331b
Update Hello World example, demonstrate synthesis 2020-03-20 10:16:40 +01:00
Xiretza c4a71b39dd
Misc updates, add core and SoC docs 2020-03-01 17:13:51 +01:00
Xiretza 9d04e5ca2b
Update gitignore 2020-02-28 18:35:54 +01:00
Xiretza ae4c533320
Add bibliography 2020-02-28 18:35:10 +01:00
Xiretza 38e12fa78b
Add Makefile and VHDL headers generation 2020-02-28 11:21:08 +01:00
Xiretza 387e9d61c6
Add initial outline of DS 2019-12-10 15:32:02 +01:00
Xiretza 3b360e3237
Move sample DS 2019-12-10 14:23:44 +01:00
Xiretza b9fa071e76
Initial import 2019-09-20 17:32:06 +02:00
Tyrolyean 35b62c8251
Adeed tex files for dipl 
Signed-off-by: Tyrolyean <tyrolyean@tyrolyean.net>
 2019-09-07 18:15:15 +02:00
Tyrolyean bb9d39a95d
Added correction and corrected version 
as given by the allmighty XH. All behail him!

Signed-off-by: Tyrolyean <tyrolyean@tyrolyean.net>
 2019-07-01 23:41:19 +02:00
Tyrolyean 6e711be18f
Added initial antrag 
Signed-off-by: Tyrolyean <tyrolyean@tyrolyean.net>
 2019-07-01 23:40:11 +02:00
Tyrolyean b7fae59d8e
INITIAL COMMIT 
Signed-off-by: Tyrolyean <tyrolyean@tyrolyean.net>
 2019-07-01 23:38:26 +02:00