Release batman-2020-03-27

This commit is contained in:
Xiretza 2020-03-27 12:51:39 +01:00
parent ad723217ad
commit 8492d24c27
Signed by: xiretza
GPG key ID: E51A6C6A1EB378ED
12 changed files with 280 additions and 0 deletions

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Diplomschrift.pdf Normal file

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entity alu is
port (
clk : in std_logic;
enable_math : in std_logic;
valid : out std_logic;
operation : in alu_operation_t;
a, b : in yarm_word;
math_result : out yarm_word;
-- compare inputs
-- do signed comparisons
enable_cmp : in std_logic;
cmp_signed : in std_logic;
cmp1, cmp2 : in yarm_word;
cmp_result : out compare_result_t
);
end alu;

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entity control is
generic (
RESET_VECTOR : yarm_word
);
port (
clk : in std_logic;
reset : in std_logic;
fetch_enable : out std_logic;
fetch_ready : in std_logic;
fetch_instr_out : in yarm_word;
decoder_enable : out std_logic;
decoder_instr_info_out : in instruction_info_t;
registers_data_a : in yarm_word;
registers_data_b : in yarm_word;
alu_enable_math : out std_logic;
alu_math_result : in yarm_word;
alu_valid : in std_logic;
alu_enable_cmp : out std_logic;
alu_cmp_result : in compare_result_t;
csr_enable : out std_logic;
csr_ready : in std_logic;
csr_data_read : in yarm_word;
csr_increase_instret : out std_logic;
datamem_enable : out std_logic;
datamem_ready : in std_logic;
alignment_raise_exc : out std_logic;
alignment_exc_data : out exception_data_t;
registers_read_enable : out std_logic;
registers_write_enable : out std_logic;
-- TRAP CONTROL
may_interrupt : out std_logic;
-- the stage that will receive an interrupt exception
interrupted_stage : out pipeline_stage_t;
do_trap : in std_logic;
trap_vector : in yarm_word;
trap_return_vec : in yarm_word;
return_trap : out std_logic;
-- instruction info records used as input for the respective stages
stage_inputs : out pipeline_frames_t
);
end control;

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entity core is
generic (
HART_ID : natural;
RESET_VECTOR : yarm_word := (others => '0')
);
port (
clk : in std_logic;
reset : in std_logic;
-- little-endian memory interface, 4 byte address alignment
MEM_addr : out yarm_word;
MEM_read : out std_logic;
MEM_write : out std_logic;
MEM_ready : in std_logic;
MEM_byte_enable : out std_logic_vector(3 downto 0);
MEM_data_read : in yarm_word;
MEM_data_write : out yarm_word;
external_int : in std_logic;
timer_int : in std_logic;
software_int : in std_logic
);
end core;

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entity csr is
generic (
HART_ID : integer
);
port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
ready : out std_logic;
instr_info_in : in instruction_info_t;
data_write : in yarm_word;
data_read : out yarm_word;
increase_instret : in std_logic;
external_int : in std_logic;
timer_int : in std_logic;
software_int : in std_logic;
interrupts_pending : out yarm_word;
interrupts_enabled : out yarm_word;
global_int_enabled : out std_logic;
mtvec_out : out yarm_word;
mepc_out : out yarm_word;
do_trap : in std_logic;
return_m_trap : in std_logic;
mepc_in : in yarm_word;
mcause_in : in yarm_trap_cause;
mtval_in : in yarm_word;
raise_exc : out std_logic;
exc_data : out exception_data_t
);
end csr;

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entity decoder is
port (
clk : in std_logic;
enable : in std_logic;
async_addr_rs1 : out register_addr_t;
async_addr_rs2 : out register_addr_t;
alu_muxsel_a : out mux_selector_t;
alu_muxsel_b : out mux_selector_t;
alu_muxsel_cmp2 : out mux_selector_t;
csr_muxsel_in : out mux_selector_t;
instr_info_in : in instruction_info_t;
instr_info_out : out instruction_info_t;
raise_exc : out std_logic;
exc_data : out exception_data_t
);
end decoder;

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entity exception_control is
port (
clk : in std_logic;
fetch_raise_exc : in std_logic;
fetch_exc_data : in exception_data_t;
-- synchronous exceptions
decoder_raise_exc : in std_logic;
decoder_exc_data : in exception_data_t;
csr_raise_exc : in std_logic;
csr_exc_data : in exception_data_t;
alignment_raise_exc : in std_logic;
alignment_exc_data : in exception_data_t;
datamem_raise_exc : in std_logic;
datamem_exc_data : in exception_data_t;
-- interrupts
global_int_enabled : in std_logic;
interrupts_enabled : in yarm_word;
interrupts_pending : in yarm_word;
-- stage inputs for return address + trap value (instruction)
stage_inputs : in pipeline_frames_t;
interrupted_stage : in pipeline_stage_t;
may_interrupt : in std_logic;
do_trap : out std_logic;
trap_cause : out yarm_trap_cause;
trap_address : out yarm_word;
trap_value : out yarm_word
);
end exception_control;

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entity memctl is
port (
addr : in yarm_word;
-- data width
data_width : in datum_width_t;
-- perfom sign extension when reading short data
sign_extend : in std_logic;
data_read : out yarm_word;
data_write : in yarm_word;
MEM_addr : out yarm_word;
MEM_byte_enable : out std_logic_vector(3 downto 0);
MEM_data_read : in yarm_word;
MEM_data_write : out yarm_word
);
end memctl;

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entity memory_arbiter is
port (
clk : in std_logic;
reset : in std_logic;
fetch_enable : in std_logic;
fetch_ready : out std_logic;
fetch_address : in yarm_word;
fetch_instr_out : out yarm_word;
fetch_raise_exc : out std_logic;
fetch_exc_data : out exception_data_t;
datamem_enable : in std_logic;
datamem_ready : out std_logic;
datamem_instr_info_in : in instruction_info_t;
datamem_read_data : out yarm_word;
datamem_raise_exc : out std_logic;
datamem_exc_data : out exception_data_t;
-- little-endian memory interface, 4 byte address alignment
MEM_addr : out yarm_word;
MEM_read : out std_logic;
MEM_write : out std_logic;
MEM_ready : in std_logic;
MEM_byte_enable : out std_logic_vector(3 downto 0);
MEM_data_read : in yarm_word;
MEM_data_write : out yarm_word
);
end memory_arbiter;

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entity multiplier is
generic (
-- A shorter than B: faster, but wider adder required
WIDTH_A : positive;
WIDTH_B : positive
--PARALLELISM : positive
);
port (
clk : in std_logic;
run : in std_logic;
valid : out std_logic;
mul_signed : in std_logic;
a : in std_logic_vector(WIDTH_A-1 downto 0);
b : in std_logic_vector(WIDTH_B-1 downto 0);
result : out std_logic_vector(WIDTH_A+WIDTH_B-1 downto 0)
);
end multiplier;

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entity program_counter is
port (
clk : in std_logic;
reset : in std_logic;
operation : in pc_operation_t;
pc_in : in yarm_word;
pc_out : out yarm_word
);
end program_counter;

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entity registers is
port (
clk : in std_logic;
read_enable : in std_logic;
write_enable : in std_logic;
addr_a : in register_addr_t;
addr_b : in register_addr_t;
addr_d : in register_addr_t;
data_a : out yarm_word;
data_b : out yarm_word;
data_d : in yarm_word
);
end registers;