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d624673804
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Add liteeth core
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2022-06-04 21:51:28 +02:00 |
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e7087eb7db
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makefile: switch to nextpnr toolchain
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2022-06-04 21:19:37 +02:00 |
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608c17d1a8
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makefile: use relative paths
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2022-06-04 21:19:26 +02:00 |
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8257886f6b
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Add nextpnr-xilinx makefile
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2022-06-04 21:18:57 +02:00 |
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63557ba83f
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fix(Makefile.symbiflow): fix read_verilog yosys command
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2022-06-03 22:18:09 +02:00 |
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eedf254b15
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fix(gen_liteeth): fix configurations
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2022-06-03 22:17:13 +02:00 |
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d6687786a7
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Add basic tools and VHDL skeleton
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2022-06-03 19:11:07 +02:00 |
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5a9bb94922
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Initial empty commit
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2022-05-11 18:15:30 +02:00 |
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