36 lines
810 B
VHDL
36 lines
810 B
VHDL
entity csr is
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generic (
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HART_ID : integer
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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enable : in std_logic;
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ready : out std_logic;
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instr_info_in : in instruction_info_t;
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data_write : in yarm_word;
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data_read : out yarm_word;
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increase_instret : in std_logic;
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external_int : in std_logic;
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timer_int : in std_logic;
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software_int : in std_logic;
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interrupts_pending : out yarm_word;
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interrupts_enabled : out yarm_word;
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global_int_enabled : out std_logic;
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mtvec_out : out yarm_word;
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mepc_out : out yarm_word;
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do_trap : in std_logic;
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return_m_trap : in std_logic;
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mepc_in : in yarm_word;
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mcause_in : in yarm_trap_cause;
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mtval_in : in yarm_word;
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raise_exc : out std_logic;
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exc_data : out exception_data_t
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);
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end csr; |