18 lines
386 B
VHDL
18 lines
386 B
VHDL
entity alu is
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port (
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clk : in std_logic;
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enable_math : in std_logic;
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valid : out std_logic;
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operation : in alu_operation_t;
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a, b : in yarm_word;
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math_result : out yarm_word;
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-- compare inputs
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-- do signed comparisons
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enable_cmp : in std_logic;
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cmp_signed : in std_logic;
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cmp1, cmp2 : in yarm_word;
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cmp_result : out compare_result_t
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);
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end alu; |